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Industry Insights,Virtuoso,CoWoS

  • TSMC 3D-IC Reference Flow Supports 3D Die Stacking

    An important milestone for any new semiconductor technology is the availability of a foundry EDA reference flow. Such a milestone occurred last week (Sept. 18, 2013) as Cadence and TSMC delivered the latest Cadence 3D-IC reference flow for true 3D die stacking (right). While there has been considerable...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Sep 24 2013
  • Top Ten Cadence Community Blog Posts of 2012

    In 2012, Cadence Community bloggers turned out over 400 posts in categories including Industry Insights, Functional Verification, PCB, IC Packaging, Custom IC, System Design and Verification, RF, Low Power, Mixed Signal, Logic Design, and Digital Implementation. Below is a listing of the ten most read...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Jan 1 2013
  • TSMC Forum: An Update on 20nm, 3D-IC, and 16nm FinFETs

    TSMC, the world's largest semiconductor foundry, is thinking big when it comes to next-generation process technology. At the TSMC Open Innovation Platform (OIP) Ecosystem Forum Oct. 16, TSMC described reference flows for 20nm and for multi-die integration, and revealed that ARM and TSMC are working...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Oct 17 2012
  • TSMC-Cadence Collaboration Helps Clarify 3D-IC Ecosystem

    Perhaps the most challenging question about 3D-IC design is what gets done when, by which kind of provider. With its recently introduced chip-on-wafer-on-substrate ( CoWoS ) process, TSMC has taken a step towards clarifying what the 3D-IC ecosystem might look like. And Cadence helped refine the methodology...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Jun 4 2012
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