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Industry Insights,TLM
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CDNLive Paper Preview: RTL Performance Analysis of ARM Interconnect IP
System on chip (SoC) interconnect must meet the performance requirements of increasingly demanding, complex chips -- but traditional modeling and verification techniques don't shed much light on bandwidth and latency. A new approach to analyzing and debugging performance with ARM system IP (interconnect...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Mar 11 2013
DVCon 2013 Preview – Learn from Other Design and Verification Engineers
The Design and Verification Conference ( DVCon 2013 ) will be held Feb. 25-28 at the Doubletree Hotel in San Jose, California - and this year's program has something of interest for almost every design and verification engineer. The conference offers 12 technical sessions, 10 tutorials, two panels...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Jan 24 2013
Si2 Talk: Why System-Level Low Power is Challenging
There's a lot of interest in "system level" low power design -- but what does it really mean? "There a lot of confusion," said Pete Hardee, director of solutions marketing at Cadence, in a presentation at the recent Silicon Integration Initiative ( Si2 ) Conference. "What's...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Oct 15 2012
Webinar: New Interface Links Specman e Language to SystemC TLM Models
As the use of SystemC transaction-level models (TLM) increases in verification environments, there's a growing need to connect SystemC TLM 2.0 models to hardware verification language testbenches. A newly archived webinar details a new interface that links the Specman e language to SystemC TLM 2...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Sep 17 2012
Whitepaper: Connecting Specman e Language to SystemC TLM Models
SystemC Transaction-Level Modeling (TLM 2.0) is coming into widespread use for virtual platforms and high-level verification, but the benefits of TLM models will be limited if there's no connection to more conventional hardware verification languages. A recently published whitepaper in the Cadence...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Aug 13 2012
Open-Source SystemC Library, Simulator Provide Insights Into New IEEE 1666 Standard
There is no better way to learn about the IEEE 1666-2011 SystemC standard than to use it - and the Accellera Systems Initiative has provided an easy way to do that with version 2.3.0 of its SystemC open-source "proof of concept" library. This free offering makes it possible to create SystemC...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Jul 19 2012
Q&A: Jim Ready Discusses EDA Connection to Embedded Software Development
Few people know the embedded OS and software development tool market as well as Jim Ready - after all, he played a key role in its formation. At Ready Systems in 1981, he developed VRTX, the first commercially viable real-time operating system (RTOS). In 1999, as founder of MontaVista Software, he pioneered...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Jul 16 2012
High-Level Synthesis Users: Productivity Gains Beckon, But Learning Curve Comes First
SystemC-based high-level synthesis (HLS) tools have greatly improved in recent years and are undergoing adoption by many large semiconductor companies. But to get high productivity out of HLS, current RTL designers will first face a learning curve, according to panelists at the recent Design Automation...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Jun 25 2012
DAC 2012 Panel – Can One System Model Serve Everybody?
Can one system model ever serve the needs of system architects, hardware developers, software developers, and verification teams? Probably not, according to panelists at the Design Automation Conference (DAC 2012) June 5. But panelists had some informative perspectives on the various types of models...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Jun 5 2012
DVCon 2012 Verification Paper Archive – UVM, Low Power, Mixed Signal and More!
In late April, a wealth of information on IC functional verification became available at the DVCon web site . Both papers and slides are now available for dozens of high-quality presentations given at the DVCon 2012 conference, which was held Feb. 27-March 1, 2012 in Santa Clara, California. You can...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, May 1 2012
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