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Industry Insights,SoC
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Q&A: Adam Traidman Updates Silicon IP Trends and ChipEstimate.com
As president and CEO of Chip Estimate before its 2008 acquisition by Cadence, Adam Traidman has been a front-row observer of the silicon IP business for many years. His company developed the InCyte chip planning tool, which includes an IP database to help designers predict area and performance. Today...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Feb 23 2012
Who Needs 40/100 Gigabit Ethernet SoCs?
Short answer: the cloud. Thanks to cloud computing and cloud applications, data centers are having to manage large data transfers in very short periods of time. System-on-chip (SoC) solutions that support 40/100 Gbit Ethernet (GbE) are now in demand, and for this reason, Cadence today (Feb. 21, 2012...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Feb 21 2012
Digital and Analog Verification – Round Peg in a Square Hole?
Recently I wrote about a panel discussion that looked at ways of bridging the gap between analog and digital design. This blog post resulted in a lengthy discussion in a LinkedIn group that brought up the topic of verification. One commentator noted that analog and digital designers have very different...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Feb 9 2012
Panelists: Bridging the Gap Between Analog and Digital Design
Analog and digital designers have lived in separate worlds for a long, long time. They use different methodologies and tools, and while digital design is heavily automated, analog design is not. But mixed-signal integration will force this gap to narrow, opening the door to new methodologies and better...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Feb 1 2012
Open NAND Flash Interface (ONFi 3.0) – Faster Throughput for SoC Designs
Memory is an important part of virtually every electronic system, yet it's increasingly becoming a performance bottleneck. The latest ONFi 3.0 (Open NAND Flash Interface) specification promises to ease this bottleneck for nonvolatile memory. But silicon IP support is needed to facilitate adoption...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Jan 9 2012
Three Die Stack -- A Big Step “Up” for 3D-ICs with TSVs
A major advancement in 3D-IC through-silicon via (TSV) design will be unveiled Tuesday (Dec. 13) as representatives of CEA-LETI and ST-Ericsson describe the development of a three-die stack with wide I/O memory and logic. This tapeout is the result of a collaboration between these two organizations and...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Dec 13 2011
ARM TechCon Paper: New Methodology Eases Challenges of 32/28nm Designs
The 32nm and 28nm process nodes, the most advanced nodes currently in production, pose formidable challenges in complexity, power management, variability, and manufacturability. A recent ARM TechCon paper authored by Cadence and Samsung described a methodology that can resolve those challenges. And it's...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Nov 9 2011
DDR PHY Interface (DFI 3.0) Spec – Freedom of Choice for SoC Design
To implement DDR4 memory in a system-on-chip, you'll need both memory controller IP and PHY IP. If there's a standard interface between the two, you won't be locked into a particular controller/PHY combination for future designs. That's why the newly released DDR PHY Interface (DFI 3...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Sep 19 2011
Seminar: Top 10 Essential System on Chip (SoC) Interfaces
What are the most important system on chip (SoC) interfaces that design and verification engineers need to understand? A "top ten" list presented at the August 25 Verification IP (VIP) seminar at Cadence included some old standbys and some new and emerging interface specifications. The list...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Aug 28 2011
Q&A: Jim McCanny Discusses Altos Design and Fast IP Characterization
In May 2011 Cadence announced the acquisition of Altos Design Automation , a provider of ultra-fast characterization tools that model timing, noise, power, and process variations for "foundation" IP (standard cells, I/Os, memories). In this interview Jim McCanny, co-founder and former CEO of...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Jul 5 2011
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