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Industry Insights,EE Times

EE Times Webinar: Verifying ARM ACE Cache-Coherent Interconnects with UVM

Cache-coherent interconnect is a key component of any SoC that uses the ARM AMBA 4 Coherency Extension ( ACE ) specification. It's hard to design and even harder to verify. A recently archived EE Times webinar shows why cache-coherent interconnect is so complex, and explains how to build a Universal...

Posted to Industry Insights (Weblog) by rgoering on Wed, Dec 5 2012
Cadence, ARM and TSMC Reveal 20nm Challenges and Solutions

At a recently archived EE Times webinar May 1, representatives of Cadence, ARM and TSMC noted three important points about the 20nm process node. Number one, its adoption is inevitable. Number two, the design and manufacturing challenges are significant. Number three, the challenges are manageable given...

Posted to Industry Insights (Weblog) by rgoering on Wed, May 2 2012
Webinar: Easing the Pain of FPGA-Based Prototyping

Nearly every digital system-on-chip, ASIC or ASSP is prototyped in FPGAs, most typically for pre-silicon software development and debugging. The problem is that it can take months to get the prototype up and running with a functionally equivalent design. But there are easier ways to develop FPGA-based...

Posted to Industry Insights (Weblog) by rgoering on Thu, Sep 8 2011
Why Cadence Bought Azuro – A Closer Look

Cadence announced July 12 its acquisition of Azuro , a provider of "clock concurrent optimization technology" (ccopt). But why, given that Cadence already has clock tree synthesis inside the Encounter Digital Implementation Platform? The answer is that Azuro technology goes far beyond clock...

Posted to Industry Insights (Weblog) by rgoering on Sun, Jul 24 2011
Panelists: A Reality Check on Hardware/Software Co-Design and Co-Verification

Is hardware/software co-development ready for prime time? Yes, but much remains to be done, according to panelists at the May 12 EE Times System on Chip "Virtual Event." Panelists discussed hardware/software partitioning, benefits of co-design and co-verification, barriers to adoption, what's...

Posted to Industry Insights (Weblog) by rgoering on Mon, May 16 2011
Panelists Discuss Solutions to SoC IP Integration Challenges

Semiconductor intellectual property (IP) reuse makes system-on-chip (SoC) design possible, but complex SoCs pose some really tough IP integration challenges. Panelists at the May 12 EE Times System on Chip "Virtual Event" answered five questions posed by moderator Mike Demler, technical editor...

Posted to Industry Insights (Weblog) by rgoering on Sun, May 15 2011
SoC Panelists: How to Overcome IP Integration Challenges

Integrating silicon IP into systems-on-chip is a lot harder than it used to be - but there are some emerging trends that will help, according to panelists at the EE Times System-on-Chip 2.0 virtual conference Nov. 18. Three topics stood out for me - the emergence of IP subsystems, the avoidance of multiple...

Posted to Industry Insights (Weblog) by rgoering on Sun, Nov 21 2010
OpenAccess – So Much To Celebrate, So Much To Do

Two distinct messages emerged from the Silicon Integration Initiative (Si2) OpenAccess Conference last week. One is that the OpenAccess database is a great EDA standards success story, perhaps the biggest such story of all. Another is that there’s still a lot of work to do so OpenAccess can offer...

Posted to Industry Insights (Weblog) by rgoering on Mon, Oct 19 2009
Impressions From A “Virtual” SoC Conference

I attended portions of an EE Times “virtual” system-on-chip (SoC) conference last week, and came away with some observations that I’d like to share. There is some irony here. After years of writing about Cadence and other EDA vendors for EE Times, I am now reporting about an EE Times...

Posted to Industry Insights (Weblog) by rgoering on Mon, Sep 21 2009
Survey Shows Reasons For Internal EDA Tool Use

Internal EDA tools can fill some important gaps in the hardware design ecosystem, according to a recent email survey sent to members of the Cadence Community . In the survey, 256 respondents first indicated whether or not they use internal CAD tools. Those who said they did – about one-third of...

Posted to Industry Insights (Weblog) by rgoering on Wed, Jun 24 2009

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Industry Insights,EE Times

EE Times Webinar: Verifying ARM ACE Cache-Coherent Interconnects with UVM

Cadence, ARM and TSMC Reveal 20nm Challenges and Solutions

Webinar: Easing the Pain of FPGA-Based Prototyping

Why Cadence Bought Azuro – A Closer Look

Panelists: A Reality Check on Hardware/Software Co-Design and Co-Verification

Panelists Discuss Solutions to SoC IP Integration Challenges

SoC Panelists: How to Overcome IP Integration Challenges

OpenAccess – So Much To Celebrate, So Much To Do

Impressions From A “Virtual” SoC Conference

Survey Shows Reasons For Internal EDA Tool Use