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Industry Insights,ARM,20nm

Common Platform Forum Keynotes: 14nm FinFETs and Beyond

How far can we continue to scale semiconductors? 14nm FinFET technology is the next major move, but that's far from the end of the story, according to keynote speakers at the Common Platform Technology Forum in Santa Clara, California Feb. 5, 2013. The keynotes, still available for on-line viewing...

Posted to Industry Insights (Weblog) by rgoering on Wed, Feb 6 2013
Video, Presentation – Low Power Design with ARM Physical and Processor IP

Most system-on-chip designers have two things in common - use of ARM physical and/or processor IP, and a mandate to reduce power consumption. There's a wealth of information on low-power design with ARM IP in a newly available video, as well as presentation slides, from an hour-long presentation...

Posted to Industry Insights (Weblog) by rgoering on Mon, Dec 17 2012
ARM Blog Tells Story of a 20nm Cortex-M0 Test Chip

All 20nm test chips are learning experiences, and a recent tapeout of a 20nm Cortex-M0 test chip by ARM engineers was no exception. Completed in June 2012, the test chip design used a Cadence digital implementation flow. The story of the test chip is told in a new guest partner blog (I'm the "guest"...

Posted to Industry Insights (Weblog) by rgoering on Tue, Nov 27 2012
ARM TechCon: Design at 14nm (or 10nm) – What’s Going to Change

The next semiconductor process node after 20nm promises tremendous power and performance benefits, but also poses some new challenges, according to a presentation by ARM and IBM at the ARM TechCon conference Oct. 30, 2012. The presentation showed how the "second generation" of double patterning...

Posted to Industry Insights (Weblog) by rgoering on Fri, Nov 2 2012
TSMC Forum: An Update on 20nm, 3D-IC, and 16nm FinFETs

TSMC, the world's largest semiconductor foundry, is thinking big when it comes to next-generation process technology. At the TSMC Open Innovation Platform (OIP) Ecosystem Forum Oct. 16, TSMC described reference flows for 20nm and for multi-die integration, and revealed that ARM and TSMC are working...

Posted to Industry Insights (Weblog) by rgoering on Wed, Oct 17 2012
IP Talks! Video – ARM’s John Heinlein Cites SoC Success Requirements

John Heinlein, vice president of marketing for the Physical IP division at ARM, believes that an advanced system-on-chip (SoC) design shouldn't be a "leap of faith." In a keynote speech at the IP Talks! sessions at the ChipEstimate.com booth at the Design Automation Conference (DAC 2012...

Posted to Industry Insights (Weblog) by rgoering on Tue, Jul 10 2012
DAC 2012 Panelists: How to Succeed at 28nm, 20nm and 14nm

What will it take to achieve silicon success at 28nm and below? That was the question put to a panel of experts at a Cadence-sponsored breakfast at the Design Automation Conference ( DAC 2012 ) June 6, where speakers from IBM, Cadence, ARM, Samsung, and GLOBALFOUNDRIES shed new light on business and...

Posted to Industry Insights (Weblog) by rgoering on Tue, Jun 12 2012
12 Hot EDA Topics – 78 DAC Demo Sessions

Whatever your role in the chip or system design process, there is probably a Cadence demo geared to your interests at the Design Automation Conference ( DAC 2012 ) June 3-7 in San Francisco. Cadence has three demo suites at its booth (#1930) and is running one-hour demos from 10:00 am to 5:00 pm Monday...

Posted to Industry Insights (Weblog) by rgoering on Thu, May 24 2012
Cadence, Samsung Detail 20nm RTL-to-GDSII Methodology

In a recently archived May 2 webinar , speakers from Cadence and Samsung described a 20nm digital design methodology that can manage challenges such as double patterning, variability, and complexity. The webinar discussed EDA tools, physical IP, and 20nm process technologies, and it highlighted a "proof...

Posted to Industry Insights (Weblog) by rgoering on Mon, May 7 2012
TSMC CDNLive! Keynote – “We Can Beat Moore’s Law”

The world's largest foundry provider, TSMC, is confident it can keep up with the semiconductor scaling predicted by Moore's Law and can even outpace Moore's Law through 2.5D and 3D-ICs. It's all part of the "incredible high-tech future" predicted by Rick Cassidy, president of...

Posted to Industry Insights (Weblog) by rgoering on Wed, Mar 14 2012

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Industry Insights,ARM,20nm

Common Platform Forum Keynotes: 14nm FinFETs and Beyond

Video, Presentation – Low Power Design with ARM Physical and Processor IP

ARM Blog Tells Story of a 20nm Cortex-M0 Test Chip

ARM TechCon: Design at 14nm (or 10nm) – What’s Going to Change

TSMC Forum: An Update on 20nm, 3D-IC, and 16nm FinFETs

IP Talks! Video – ARM’s John Heinlein Cites SoC Success Requirements

DAC 2012 Panelists: How to Succeed at 28nm, 20nm and 14nm

12 Hot EDA Topics – 78 DAC Demo Sessions

Cadence, Samsung Detail 20nm RTL-to-GDSII Methodology

TSMC CDNLive! Keynote – “We Can Beat Moore’s Law”