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Industry Insights

  • Panel Question: Should Designers Do Their Own Verification?

    One question that prompted a lively discussion at the recent Cadence Mixed-Signal Design Summit was whether design engineers should do their own verification. This is a particularly good question for analog and mixed-signal design, where the tradition of separate verification teams is not as strong as...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Nov 11 2009
  • “Software Signoff” Raises Many Questions

    At a discussion at the ICCAD conference last week, EDA notables Jim Hogan and Paul McLellan talked about “ what EDA needs to change for 2020 success. ” One topic they emphasized is “software signoff,” and they encouraged those present – mostly bloggers – to go forth...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Nov 9 2009
  • DFT Challenge: Evaluating The True Cost Of Test

    Remember DFT? “Design For Test” faded into the background in recent years as the industry turned its focus to DFM, but if anything test is an even larger concern than it was 10 or 15 years ago. That’s because test is becoming more difficult and expensive at nanometer process nodes,...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Nov 5 2009
  • Greatest Moments In EDA Innovation

    Innovation is the lifeblood of the EDA industry, and it is only because of innovation from many sources – including academia and industry – that modern IC design is possible at all. Today at Cadence (Nov. 3, 2009), we are celebrating Cadence Innovation Day . As such, it seems like a good...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Nov 3 2009
  • Users Outline New Approaches To Mixed-Signal Verification

    At the Cadence Mixed-Signal Design Summit , held Oct. 27, I had a hard time finding a seat in a packed auditorium. One reason for the summit’s popularity was its hands-on, practical nature. A series of user presentations showed how designers are solving real problems in mixed-signal verification...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Nov 2 2009
  • User Interview: How To Estimate Power Early

    Early power estimation makes it much easier to manage IC power, according to Camille Kokozaki, director of design automation services at Integrated Device Technology ( IDT ). At the recent CDNLive! Silicon Valley , he presented a case study of architectural power estimation with a 65nm system-on-chip...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Oct 29 2009
  • Panelists: 32 nm HKMG Is Ready To Roll

    The 32/28 nm Common Platform high-k metal gate (HKMG) technology is “ready and open for business,” according to the title of a breakfast panel at the ARM Techcon3 conference Oct. 22. Panelists from IBM , ARM and Cadence talked about the benefits of HKMG, the requirements it places on the...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Oct 28 2009
  • Panelists Broaden Scope Of Low-Power Discussion

    Most of the discussion about low-power design has centered around the RTL-to-GDSII flow for digital ICs. But the real problem is much broader, according to panelists from AMD , Sonics , Wipro , and Cadence at the recent Power Forward Initiative (PFI) Low-Power Design Summit Oct. 20. Entitled “The...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Oct 26 2009
  • User Interview: An Under The Hood Look At PDKs

    Well-made process design kits (PDKs) are critical for successful IC design, and design teams should keep in touch with PDK technology development, according to Kristin Liu, principal CAD engineer at National Semiconductor . In an interview at the recent CDNLive! Silicon Valley , she talked about the...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Oct 22 2009
  • Cadence’s Andreas Kuehlmann To Head IEEE Council On EDA

    With a deep involvement in conferences, publications, educational programs and awards, the IEEE Council on EDA ( CEDA ) is a behind-the-scenes organization that has a large influence on the professional EDA community. Andreas Kuehlmann, Cadence fellow and director of Cadence Research Labs , will become...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Oct 21 2009
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