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  • Place and route on SOC encounter

    Hello, I am a newbie at place and route operation. Can anyone please tell me how do you make sure that all the blockes i your design are arranged in a certain way while doing place and route . I mean I have like around 300 odd blockes to be eranged and I want them to be ordered row wise and column wise...
    Posted to Digital Implementation (Forum) by amythpai on Sun, Mar 17 2013
  • Via Placement issue.

    Hi every one, I'm Lakshmi Prashanth, and i'm new to this encounter tool, I've got a problem., initially when i was moving the PG net over the Macros, tool was automatically placing the via's, But suddenly yesterday, some via's are deleted automatically, I don't know how, and If...
    Posted to Digital Implementation (Forum) by Leader on Tue, Feb 12 2013
  • Tech-On-Tour: Bringing Advanced Mixed-Signal Design Methodology from Concepts to Reality

    About a year ago, Cadence offered a worldwide Tech-On-Tour (ToT) series for mixed-signal designs. One main objective of this seminar series is to bring the awareness of the need for a design methodology change to the broad mixed-signal designer community worldwide. The event was very successful and you...
    Posted to Mixed-Signal Design (Weblog) by QiWang on Tue, Jun 19 2012
  • Problems Importing OA Design from Virtuoso into Encounter

    Hello, While trying to perform place and route using Encounter I'm "encountering" errors importing my design from Virtuoso. When I try to import the design, I get the following: Reading tech data from OA Library 'NCL' ... FE units: 0.001 microns/dbu, OA units: 0.001 microns/dbu...
    Posted to Digital Implementation (Forum) by TruLogic on Mon, Jan 10 2011
  • User Interview: How To Estimate Power Early

    Early power estimation makes it much easier to manage IC power, according to Camille Kokozaki, director of design automation services at Integrated Device Technology ( IDT ). At the recent CDNLive! Silicon Valley , he presented a case study of architectural power estimation with a 65nm system-on-chip...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Oct 29 2009
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