	Login with a Cadence account.
Not a member yet? Create a permanent login account to make interactions with Cadence more conveniennt. Register \| Membership benefits

Get email delivery of the Cadence blog (individual posts).

Popular Tags

Browse All Tags

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Send yourself a copy

Cadence RSS Feeds

Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.

Contact Us

Cadence Contacts

Global Office Locator
Find Offices worldwide »

Sales Inquiry
Request for Product information »
Cadence Channel Partners »

Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Send Yourself A Copy

Incisive

UVM SystemVerilog Class Library Overview Video – Inspired by 1600 Cowbells in Action

Just after releasing the original cowbell video series I found that Ben and Jerry's had discovered a great way to combine cowbells and charity. In April of this year, they held an event for a new world record of over 1600 cowbells in action . It is a must see for the cowbell aficionado. Coincidentally...

Posted to Functional Verification (Weblog) by Axel Scherer on Mon, Jul 16 2012
My Clark Kent Moment – How I Discovered Aspect Oriented Programming in e (IEEE 1647)

Growing up on VHDL, moving on to Verilog and then to SystemVerilog, I eventually discovered e (IEEE 1647) Initially I thought: "What is the fuss all about?" While exploring the language during the development of the cowbell videos , it hit me -- I started to recognize the power of Aspect Oriented...

Posted to Functional Verification (Weblog) by Axel Scherer on Tue, Jul 10 2012
Using Flexible Specman License Searches

Until recently, Specman used to look for its licenses in the following strict, hardcoded order: Either 1. "Incisive Specman Elite" 2. "Incisive Enterprise Simulator" 3. "Incisive Enterprise Verifier" Or 1. "Incisive Enterprise Simulator" 2. "Incisive Enterprise...

Posted to Functional Verification (Weblog) by teamspecman on Mon, Jul 9 2012
Re: Linking the library doesn't work properly at co-verification

I am able to fix it by compiling the SystemC model files (work_dut_sc) into the loading dynamic object ( work_sc itself) at final elaboration. Like, in the irun command, there is a option -loadsc which takes the final linked object to be loaded. So i compiled into the same object and able to simulate...

Posted to Hardware/Software Co-Development, Verification and Integration (Forum) by Coverification on Tue, Jun 19 2012
Linking the library doesn't work properly at co-verification

The following are the flow in the environment: 1) Testbennch top at SystemC -> Compiled separately and kept in work_sc folder with specific dynamic library linking (-test) using ncsc_run command. 2) Design in VHDL with quite lot of internal modules. -> Compiled and kept in work_dut and link all...

Posted to Hardware/Software Co-Development, Verification and Integration (Forum) by Coverification on Mon, Jun 18 2012
SC_TIMESCALE

Hi, What is the significance of SC_TIMESCALE and how it affects the global timescale if SystemC module is instantiated in Top level SystemVerilog module. Documentation for SC_TIMESCALE is not available in installation path.

Posted to Hardware/Software Co-Development, Verification and Integration (Forum) by ravi999 on Thu, Jun 7 2012
Being The Energizer Bunny at DAC … Championing System-Level Design and Verification ;)

As the EDA industry and its customers are preparing for the yearly show down at the Design Automation Conference (DAC), it is good to review what I said in the past. Well, two years ago I wrote a blog called "Maybe This Time" ( inspired by the Sally Bowles song in Cabaret , I am a Musical Geek...

Posted to System Design and Verification (Weblog) by fschirrmeister on Fri, Jun 1 2012
Inefficiency is Futile – Gain UVM e and SystemVerilog Verification Productivity Using Save, Restore, and Reseed

In the world of Star Trek " resistance is futile " when you encounter the Borg . Fortunately, in verification we do not have to deal with the Borg. Nonetheless, our world provides plenty of challenges. Schedules are tight, problems are complex, and market windows are narrow. In other words...

Posted to Functional Verification (Weblog) by Axel Scherer on Fri, Jun 1 2012
Get Started on UVM-e with Free Introductory Video Tutorials

One of the many requests that we get from Specman/ e customers is that they would like some basic e tutorials. So, as a first step, Axel Scherer has recently posted 24, very short, byte sized UVM- e basic tutorials . Check them out. These e -based videos are targeted for design and verification engineers...

Posted to Functional Verification (Weblog) by teamspecman on Thu, May 24 2012
Tips on Writing Macros in Specman e Language

In this blog, I will present some tips that can be very useful when you write e macros. We will see which kind of macro we should use for our purposes, and what options we can use to better define our macro. Let's begin by looking at the following simple example. Assume that you want to define a...

Posted to Functional Verification (Weblog) by teamspecman on Tue, May 22 2012

Page 5 of 21 (205 items) « First ... < Previous 3 4 5 6 7 Next > ... Last »

Popular Tags

Email

Share

Subscribe

Contact Us

Incisive

UVM SystemVerilog Class Library Overview Video – Inspired by 1600 Cowbells in Action

My Clark Kent Moment – How I Discovered Aspect Oriented Programming in e (IEEE 1647)

Using Flexible Specman License Searches

Re: Linking the library doesn't work properly at co-verification

Linking the library doesn't work properly at co-verification

SC_TIMESCALE

Being The Energizer Bunny at DAC … Championing System-Level Design and Verification ;)

Inefficiency is Futile – Gain UVM e and SystemVerilog Verification Productivity Using Save, Restore, and Reseed

Get Started on UVM-e with Free Introductory Video Tutorials

Tips on Writing Macros in Specman e Language