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Incisive

Tips on Writing Macros in Specman e Language

In this blog, I will present some tips that can be very useful when you write e macros. We will see which kind of macro we should use for our purposes, and what options we can use to better define our macro. Let's begin by looking at the following simple example. Assume that you want to define a...

Posted to Functional Verification (Weblog) by teamspecman on Tue, May 22 2012
UVM e (IEEE 1647) Video Series Features the Return of the Cowbell!

A significant number of readers of my previous post on this topic were not aware of the Saturday Night Live cowbell skit. This took me quite by surprise! The only prescription for this problem is that I pledge to continue to play the cultural ambassador and will introduce more vital trivia! However,...

Posted to Functional Verification (Weblog) by Axel Scherer on Mon, May 21 2012
How Debug Breakthroughs are Enabled by In-Circuit Acceleration

We in product management are often accused of jumping the gun and announcing products too fast. Users are looking at press releases and are wondering "sounds great, but does it really work?" Cadence announced earlier this week new in-circuit acceleration capabilities to our System Development...

Posted to System Design and Verification (Weblog) by fschirrmeister on Wed, May 16 2012
In-Circuit Acceleration – A New IC Verification Use Model

Last year Cadence introduced the System Development Suite , a set of four connected hardware/software co-development platforms. Today (May 15, 2012) Cadence is announcing a new release of the System Development Suite that is highlighted by a new verification use model called in-circuit acceleration....

Posted to Industry Insights (Weblog) by rgoering on Tue, May 15 2012
American Technology Awards - Finally I Can Explain to my Mom What I am Actually Working On!

I think all of us engineers have faced at one point or another the need to explain to our parents or friends what we are actually working on. Hey Mom, EDA is where electronics begins! Without us electronics would not change our day to day lives ... Punctually for Mothers day, which I spent with my Mom...

Posted to System Design and Verification (Weblog) by fschirrmeister on Mon, May 14 2012
Specman’s Memory Management Orientation Guide (or “Honey – Please Take out the Garbage”)

Memory management is not something the Specman user is supposed to worry about. Nobody likes to make notes about allocations and freeing up memory segments when he's programming, and Specman supplies a mechanism that allows the programmer to have some extra time for a cup of coffee. Unfortunately...

Posted to Functional Verification (Weblog) by teamspecman on Fri, May 11 2012
UVM SystemVerilog Video Series Brings Verification World "More Cowbell!"

To quote an American pop culture catchphrase made famous by Saturday Night Live character Bruce Dickison , "I gotta have more cowbell !" In the world of functional verification this translates to "more collateral!" Thererfore, we have released a set of byte-size videos about the basics...

Posted to Functional Verification (Weblog) by Axel Scherer on Thu, May 3 2012
Gentlemen, Start Your Simulation Engines

As we outlined in our recent performance white paper , every verification team has the need for higher performance simulation. Of course, you can expect on-going innovation from Cadence R&D, but there are some things you can do to get more from your engine at any time. The February 23, 2012 webinar...

Posted to Functional Verification (Weblog) by Adam Sherilog on Wed, Feb 22 2012
Whitepaper: Verification Performance is More Than Raw Simulation Speed

RTL and gate-level simulation have been the workhorses of the IC verification environment for 25 years, and they're orders of magnitude faster than they used to be. But as chip complexity skyrockets and process nodes shrink, a continuous cry arises from verification teams - "make it faster,...

Posted to Industry Insights (Weblog) by rgoering on Tue, Jan 31 2012
Incisive Performance Scales to Meet Advanced Node SoC Verification Requirements

Its’ all about RTL simulation. I mean gates. I mean turn-around-time. Project-level productivity. Mixed-signal. Low-power. UVM. And. And. And. … And the reality is that advanced node SoCs are so complex that it is truly about all of these. Our new white paper details a systematic approach...

Posted to Functional Verification (Weblog) by Adam Sherilog on Mon, Jan 30 2012

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Incisive

Tips on Writing Macros in Specman e Language

UVM e (IEEE 1647) Video Series Features the Return of the Cowbell!

How Debug Breakthroughs are Enabled by In-Circuit Acceleration

In-Circuit Acceleration – A New IC Verification Use Model

American Technology Awards - Finally I Can Explain to my Mom What I am Actually Working On!

Specman’s Memory Management Orientation Guide (or “Honey – Please Take out the Garbage”)

UVM SystemVerilog Video Series Brings Verification World "More Cowbell!"

Gentlemen, Start Your Simulation Engines

Whitepaper: Verification Performance is More Than Raw Simulation Speed

Incisive Performance Scales to Meet Advanced Node SoC Verification Requirements