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Incisive,debugging

Improve Debug Productivity - SimVision Video Series on YouTube

Most verification customers claim that they are spending over 50% of their verification effort in debug. If so, you should check out these latest SimVision debug videos since you will quickly see how SimVision can enable you to be much more productive in less than an hour after viewing the videos. Take...

Posted to Functional Verification (Weblog) by Karnane on Tue, Feb 5 2013
Functional Verification Survey -- Why Gate-Level Simulation is Increasing

In a recent webinar on increasing functional verification performance, the point was made that gate-level simulation usage is increasing. Wait a minute, I thought - haven't we spent the last two decades talking about raising the abstraction level for design and verification? While some IC verification...

Posted to Industry Insights (Weblog) by rgoering on Wed, Jan 16 2013
Webinar Report: Speeding RTL and Gate-Level Simulation

Every verification team wants faster functional verification performance. Fortunately, there are many ways to achieve that. A recently archived Cadence webinar illustrates a number of techniques for speeding both RTL and gate-level simulation, including "out of the box" improvements to the...

Posted to Industry Insights (Weblog) by rgoering on Thu, Dec 13 2012
Archived Webinar: New Technology Attacks the Verification Debug Bottleneck

Verification debug hasn't exactly been a hotbed of technology innovation, even though verification teams report that debugging can consume more than 50% of the overall verification effort. A recently archived Cadence webinar reviews common debug challenges and shows how the new Incisive Debug Analyzer...

Posted to Industry Insights (Weblog) by rgoering on Thu, Nov 29 2012
Recorded Webinar: Using Metric-Driven Verification and Formal Together For Higher Productivity

[Preface: the upcoming " Club Formal " on October 17 here at the Cadence San Jose campus will also touch on this topic - please join us! ] While it's now common knowledge that there are many benefits to using simulation technology within a metric-driven verification (MDV) flow , as it turns...

Posted to Functional Verification (Weblog) by TeamVerify on Wed, Oct 10 2012
In-Circuit Acceleration – A New IC Verification Use Model

Last year Cadence introduced the System Development Suite , a set of four connected hardware/software co-development platforms. Today (May 15, 2012) Cadence is announcing a new release of the System Development Suite that is highlighted by a new verification use model called in-circuit acceleration....

Posted to Industry Insights (Weblog) by rgoering on Tue, May 15 2012
Whitepaper: Verification Performance is More Than Raw Simulation Speed

RTL and gate-level simulation have been the workhorses of the IC verification environment for 25 years, and they're orders of magnitude faster than they used to be. But as chip complexity skyrockets and process nodes shrink, a continuous cry arises from verification teams - "make it faster,...

Posted to Industry Insights (Weblog) by rgoering on Tue, Jan 31 2012
S4D Workshop: System, Software, SoC and Silicon Debug

Debugging is challenging at every step in system design - whether for hardware or embedded software, or at the System Realization, SoC Realization, or Silicon Realization levels. A day-long workshop at the upcoming Design Automation and Test (DATE) conference in Grenoble, France March 14 is taking an...

Posted to Industry Insights (Weblog) by rgoering on Tue, Feb 22 2011
ESL Verification News From CDNLive! EMEA

Hello from CDNLive! EMEA in Munich. Another year has passed, and it’s time again for one of the most popular CDNLive! tour stops here in EMEA. The location is the beautiful European city of Munich , at the Park Hilton Hotel . The hotel overlooks one of the largest urban parks called the English...

Posted to System Design and Verification (Weblog) by Steve Brown on Mon, May 18 2009

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Incisive,debugging

Improve Debug Productivity - SimVision Video Series on YouTube

Functional Verification Survey -- Why Gate-Level Simulation is Increasing

Webinar Report: Speeding RTL and Gate-Level Simulation

Archived Webinar: New Technology Attacks the Verification Debug Bottleneck

Recorded Webinar: Using Metric-Driven Verification and Formal Together For Higher Productivity

In-Circuit Acceleration – A New IC Verification Use Model

Whitepaper: Verification Performance is More Than Raw Simulation Speed

S4D Workshop: System, Software, SoC and Silicon Debug

ESL Verification News From CDNLive! EMEA