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Incisive,VIP

ABV
ABVIP
accelerated VIP
acceleration
ACE protocol
Amazon
AMBA
AMBA 4
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DAC 2013: User Perspectives on System-Level Verification

The best way to learn about an emerging technology is to hear from the people who are using it. If you're curious about system-level design and verification, you can do just that at the Cadence System-to-Silicon Verification Breakfast at the Design Automation Conference ( DAC 2013 ) Tuesday, June...

Posted to Industry Insights (Weblog) by rgoering on Wed, May 15 2013
Webinar Report: Assertion-Based Verification IP Ensures ARM ACE Protocol Compliance

Do you want to enjoy the benefits of formal verification without having to become an expert? A newly archived Cadence webinar shows how you can do just that, using assertion-based verification IP (ABVIP) that supports both formal and dynamic verification of systems-on-chip using the ARM ACE protocol...

Posted to Industry Insights (Weblog) by rgoering on Wed, Dec 19 2012
Interconnect Workbench Eases Analysis and Verification for ARM-Based SoCs

In today's complex SoCs, early performance analysis and verification of SoC interconnect is crucial. Architects must ensure that interconnect will meet the bandwidth and latency requirements of the target application, while verification engineers must build a testbench that assures functional correctness...

Posted to Industry Insights (Weblog) by rgoering on Tue, Oct 9 2012
Webinar Report: How Formal “Apps” Ease IC Verification

Formal verification applications, or "apps," can significantly lighten the IC verification workload without requiring a knowledge of assertion-based verification (ABV) - or even, in most cases, the need to write assertions. A recently archived Cadence webinar , held Aug. 8, 2012, describes...

Posted to Industry Insights (Weblog) by rgoering on Thu, Aug 16 2012
In-Circuit Acceleration – A New IC Verification Use Model

Last year Cadence introduced the System Development Suite , a set of four connected hardware/software co-development platforms. Today (May 15, 2012) Cadence is announcing a new release of the System Development Suite that is highlighted by a new verification use model called in-circuit acceleration....

Posted to Industry Insights (Weblog) by rgoering on Tue, May 15 2012
Archived Webinar: Bringing SystemC and C/C++ Models into UVM

If you use or plan to use C language models for verification - be they SystemC, C, or C++ -- you will probably want to connect them to a SystemVerilog verification environment. How can this be done? A newly archived Cadence webinar has the answer - use the multi-language support capability that Cadence...

Posted to Industry Insights (Weblog) by rgoering on Mon, Nov 7 2011
Video: Duolog at DAC 2011 Update – Automating Design and Verification IP Integration

One of the key tenants of the EDA360 vision is the need for scalable, correct-by-construction IP creation and integration of design and verification IP. Duolog is in the vanguard of creating automation to address this challenge, and in this video update Duolog's CTO Dave Murray notes new capabilities...

Posted to Functional Verification (Weblog) by jvh3 on Sun, Jun 26 2011
Cadence Denali Acquisition Results in Broad Verification IP (VIP) Offering

High-tech mergers succeed when two companies blend their technologies and expertise to come up with a "best of both" solution. That's the idea behind today's (Feb. 28, 2011) Cadence Verification IP (VIP) catalog announcement , which combines VIP and technology that originated at both...

Posted to Industry Insights (Weblog) by rgoering on Mon, Feb 28 2011
What Does Silicon Realization Mean for Verification Engineers?

Last May , I posed a question about what EDA360 means for verification engineers. Yesterday we made an announcement about verification for Silicon Realization that is a big deal. We are delivering a lot of new technology with immediate and high value to verification engineers everywhere. My colleagues...

Posted to Functional Verification (Weblog) by tomacadence on Tue, Jan 11 2011
"We Want UVM 1.0! When Do We Want it? Now!"

Short of holding signs and yelling slogans, the 12 customers I visited in the past week all declared this mantra. All are planning to move to UVM 1.0 with all of them requiring the phasing and register package capabilities, but only one also requiring TLM2 support, primarily for accessing SystemC models...

Posted to Functional Verification (Weblog) by Adam Sherilog on Thu, Oct 7 2010

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Incisive,VIP

DAC 2013: User Perspectives on System-Level Verification

Webinar Report: Assertion-Based Verification IP Ensures ARM ACE Protocol Compliance

Interconnect Workbench Eases Analysis and Verification for ARM-Based SoCs

Webinar Report: How Formal “Apps” Ease IC Verification

In-Circuit Acceleration – A New IC Verification Use Model

Archived Webinar: Bringing SystemC and C/C++ Models into UVM

Video: Duolog at DAC 2011 Update – Automating Design and Verification IP Integration

Cadence Denali Acquisition Results in Broad Verification IP (VIP) Offering

What Does Silicon Realization Mean for Verification Engineers?

"We Want UVM 1.0! When Do We Want it? Now!"