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Incisive Enterprise Simulator (IES),AF,Functional Verification

  • Develop For Debugability – Part II

    Looking at Coding Styles for Debug In this blog post we are going to discuss 3 different cases where coding style can help you debug easier: 1. Declarative vs. Sequential Coding 2. Method Call Depth 3. Calculating if-else Conditions Declarative vs. Sequential Coding When modeling your testbench you will...
    Posted to Functional Verification (Weblog) by teamspecman on Tue, Apr 23 2013
  • Develop for Debugability – Part 1

    Debugging is the most time-critical activity of any verification engineer. Finding a bug is very often a combination of having a good hunch, experience, and the quality of testbench code that you need to analyze. Since having a good hunch and experience is something everyone needs to acquire for themselves...
    Posted to Functional Verification (Weblog) by teamspecman on Mon, Apr 8 2013
  • Tips on Using “vhdlsync” With e+Mixed HDL Simulation

    [ Team Specman welcomes Principal Support Application Engineer Avi Farjoun to share some important tips on the famous “vhdlsync” switch] As users with mixed VHDL and Verilog environments know, even in this day & age mixed HDL simulation cycle semantics are not very well defined. Even...
    Posted to Functional Verification (Weblog) by teamspecman on Thu, Jun 11 2009
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