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Incisive Enterprise Simulator

Get Started on UVM-e with Free Introductory Video Tutorials

One of the many requests that we get from Specman/ e customers is that they would like some basic e tutorials. So, as a first step, Axel Scherer has recently posted 24, very short, byte sized UVM- e basic tutorials . Check them out. These e -based videos are targeted for design and verification engineers...

Posted to Functional Verification (Weblog) by teamspecman on Thu, May 24 2012
UVM e (IEEE 1647) Video Series Features the Return of the Cowbell!

A significant number of readers of my previous post on this topic were not aware of the Saturday Night Live cowbell skit. This took me quite by surprise! The only prescription for this problem is that I pledge to continue to play the cultural ambassador and will introduce more vital trivia! However,...

Posted to Functional Verification (Weblog) by Axel Scherer on Mon, May 21 2012
UVM SystemVerilog Video Series Brings Verification World "More Cowbell!"

To quote an American pop culture catchphrase made famous by Saturday Night Live character Bruce Dickison , "I gotta have more cowbell !" In the world of functional verification this translates to "more collateral!" Thererfore, we have released a set of byte-size videos about the basics...

Posted to Functional Verification (Weblog) by Axel Scherer on Thu, May 3 2012
Whitepaper: Verification Performance is More Than Raw Simulation Speed

RTL and gate-level simulation have been the workhorses of the IC verification environment for 25 years, and they're orders of magnitude faster than they used to be. But as chip complexity skyrockets and process nodes shrink, a continuous cry arises from verification teams - "make it faster,...

Posted to Industry Insights (Weblog) by rgoering on Tue, Jan 31 2012
Incisive Performance Scales to Meet Advanced Node SoC Verification Requirements

Its’ all about RTL simulation. I mean gates. I mean turn-around-time. Project-level productivity. Mixed-signal. Low-power. UVM. And. And. And. … And the reality is that advanced node SoCs are so complex that it is truly about all of these. Our new white paper details a systematic approach...

Posted to Functional Verification (Weblog) by Adam Sherilog on Mon, Jan 30 2012
Holiday Idea #1: Give the Gift of UVM Knowledge

Your favorite verification engineer has been good all year. Thousands of tests run. Nights and weekends of debug. So how do reward her? Why, with UVM Training , of course! Cadence experts have trained hundreds of engineers on OVM and UVM. These trainers have deep knowledge in both the methodology and...

Posted to Functional Verification (Weblog) by Adam Sherilog on Tue, Dec 6 2011
Technical Tip on How to Use HDL Assertions in e

While assertion callbacks have existed in Specman/e for several years now, several questions on their usage have surfaced recently, so here is a short refresher on their usage. ABV (Assertion Based Verification) is, more and more, becoming an important aspect of any complete verification. HDL assertions...

Posted to Functional Verification (Weblog) by teamspecman on Wed, Sep 28 2011
What Does SystemC Mean for Design and Verification?

My colleague Jack Erickson recently published in the Cadence System Design and Verification Community a blog post entitled "IP Cannot Be an Efficient Abstraction Level without SystemC!" When I saw the title, my immediate reaction was to write a complementary post called "SystemC Cannot...

Posted to Functional Verification (Weblog) by tomacadence on Tue, Aug 23 2011
Way Worse Than The Real Thing

This week Cadence and Virtutech announced a collaborative effort to bring together the Virtutech Simics virtual platform with the Cadence ISX software testing system. This is a very interesting combination of technologies, clearly demonstrating how virtual platforms make it possible to test software...

Posted to System Design and Verification (Weblog) by TeamESL on Mon, May 18 2009
ESL Verification News From CDNLive! EMEA

Hello from CDNLive! EMEA in Munich. Another year has passed, and it’s time again for one of the most popular CDNLive! tour stops here in EMEA. The location is the beautiful European city of Munich , at the Park Hilton Hotel . The hotel overlooks one of the largest urban parks called the English...

Posted to System Design and Verification (Weblog) by Steve Brown on Mon, May 18 2009

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Incisive Enterprise Simulator

Get Started on UVM-e with Free Introductory Video Tutorials

UVM e (IEEE 1647) Video Series Features the Return of the Cowbell!

UVM SystemVerilog Video Series Brings Verification World "More Cowbell!"

Whitepaper: Verification Performance is More Than Raw Simulation Speed

Incisive Performance Scales to Meet Advanced Node SoC Verification Requirements

Holiday Idea #1: Give the Gift of UVM Knowledge

Technical Tip on How to Use HDL Assertions in e

What Does SystemC Mean for Design and Verification?

Way Worse Than The Real Thing

ESL Verification News From CDNLive! EMEA