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Imperas

System to Silicon Verification – CDNLive Gives a Reality Check on How Hardware and Software Meet

Ever since switching from being a hardware/software chip developer to being an enabler with tools in EDA and embedded software, I was part of a team working towards methodologies and tools to improve the interaction of hardware and software. In December last year -- 15 years in -- I summarized a great...

Posted to System Design and Verification (Weblog) by fschirrmeister on Fri, Mar 8 2013
Update to the Linux Kernel Message System

A few months ago I wrote an Introduction to the Linux Kernel Message System . As with all software, especially Linux, things get out of date and need updating. The Linux 3.5 kernel contained changes to the kernel message system that are relevant to my previous article. I found coverage of the changes...

Posted to System Design and Verification (Weblog) by jasona on Fri, Dec 7 2012
Introduction to the Linux Kernel Message System

One of the most common problem reports related to Virtual Platforms running Linux goes something like: I run the simulation and the terminal says "Uncompressing Linux... done, booting the kernel" and nothing happens. One of my favorite books is Embedded Linux Primer: A Practical Real-World...

Posted to System Design and Verification (Weblog) by jasona on Tue, Sep 4 2012
Being The Energizer Bunny at DAC … Championing System-Level Design and Verification ;)

As the EDA industry and its customers are preparing for the yearly show down at the Design Automation Conference (DAC), it is good to review what I said in the past. Well, two years ago I wrote a blog called "Maybe This Time" ( inspired by the Sally Bowles song in Cabaret , I am a Musical Geek...

Posted to System Design and Verification (Weblog) by fschirrmeister on Fri, Jun 1 2012
Virtual Platform for Xilinx Zynq – Why “Extensible” Matters

You would expect a unique semiconductor product to have a unique software development environment. That is the case with the Xilinx Zynq-7000 family, an Extensible Processing Platform (EPP) that includes a dual-core ARM Cortex-A9 processor and a 28nm FPGA fabric. Today (Oct. 26, 2011) at ARM TechCon...

Posted to Industry Insights (Weblog) by rgoering on Wed, Oct 26 2011
Q&A: A Closer Look at the Cadence Virtual System Platform

Cadence took a significant step into a new marketplace with the recent introduction of the Virtual System Platform , a virtual prototyping environment that supports architectural-level, pre-RTL software development and debugging. The Virtual System Platform is part of the tightly integrated System Development...

Posted to Industry Insights (Weblog) by rgoering on Wed, May 25 2011
System Realization Webinars in 2010 -- A Summary

Last year was unprecedented for Cadence. We came up with the EDA360 vision , reorganized internally to align to that vision, and established some great partnerships to help our customers realize their own visions around EDA360. The ED360 vision paper has been well received by both customers and competition...

Posted to System Design and Verification (Weblog) by MayankBhatia on Fri, Jan 7 2011
Why Virtual Platforms Need Advanced Verification

By allowing software development long before silicon is available, virtual platforms (also known as "virtual prototypes" or simply "simulation") are playing an increasingly important role in electronic system development. But they're just an initial step in the next generation...

Posted to Industry Insights (Weblog) by rgoering on Thu, Sep 23 2010
System Realization Webinars Start Sept 8th

Starting September 8th Cadence will be hosting a series of webinars about various topics in the area of System Realization. Several of these webinars will be led by members of the System Realization Alliance, sharing their particular views and contributions of the industry, and their connection and interoperability...

Posted to System Design and Verification (Weblog) by Steve Brown on Tue, Aug 24 2010
Imperas Interview: Connecting Virtual Platforms To HW/SW Verification

Imperas is a provider of virtual platform technology and a member of the new Cadence System Realization Alliance . Imperas has also been doing some interesting work with Cadence that involves the integration of virtual platform models with Incisive simulation and Incisive Software Extensions . Simon...

Posted to Industry Insights (Weblog) by rgoering on Thu, Aug 12 2010

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Imperas

System to Silicon Verification – CDNLive Gives a Reality Check on How Hardware and Software Meet

Update to the Linux Kernel Message System

Introduction to the Linux Kernel Message System

Being The Energizer Bunny at DAC … Championing System-Level Design and Verification ;)

Virtual Platform for Xilinx Zynq – Why “Extensible” Matters

Q&A: A Closer Look at the Cadence Virtual System Platform

System Realization Webinars in 2010 -- A Summary

Why Virtual Platforms Need Advanced Verification

System Realization Webinars Start Sept 8th

Imperas Interview: Connecting Virtual Platforms To HW/SW Verification