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ISX,TLM

  • Virtual Flash Memory Gets Real

    This week's Flash Memory summit will not only highlight the IP Cadence delivers, but will touch on innovative application of virtual prototype technology for Flash Memory firmware and system development. Developing complex memory controllers is challenging, and an increasing portion of the capability...
    Posted to System Design and Verification (Weblog) by Steve Brown on Mon, Aug 8 2011
  • TLM Brings “ESL” Down To Earth

    Has ESL – meaning Electronic System Level, not English as a Second Language – outlived its usefulness as a label that supposedly describes the next step forward for IC and systems design? “ESL” has become a vague term that applies to many different things. A more specific term...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Jul 16 2009
  • Q&A Interview: Chris Tice Outlines Cadence System Level Design Strategy

    Chris Tice is the senior vice president and general manager for System Design and Verification at Cadence Design Systems. In this interview, he discusses upcoming and ongoing developments with transaction-level IP design, virtual platforms, embedded software verification, and system-level low power design...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Jun 8 2009
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