Log In
|
Register
|
Resource Library
|
Worldwide
Asia-Pacific
|
China
|
EMEA
|
India
|
Israel
|
Japan
|
Korea
|
Taiwan
|
Global Office Locator
Solutions
Products
Services
Support & Training
Alliances
Community
About Cadence
Solutions:
Design IP
Mixed-Signal
Low-Power
Advanced Node
Enterprise Verification
Hosted Design
System Development Suite
Solutions Home
Products for:
System Design and Verification
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Manufacturability Signoff
More Products
OrCAD Products
Design IP
Verification IP
IP Catalog
Products A-Z
Products Home
Capabilities and Practices
Methodology Services
Design Services
DFM Services
Educational Services
Programs
SOI Design Hub
Services Home
Support
Support Offerings
Support Process
Cadence Online Support
Software Downloads
Computing Platform Support
University Software Program
Training
Training Options
Training Course Catalogs
Support & Training Home
Programs and Initiatives
System Realization Alliance
Foundry Program
IP Alliances
ChipEstimate.com - Chip Planning Portal
Connections Program
Verification Alliance Program
Channel Partner (VARs) Program
Power Forward Initiative
Standards and Languages
PCB Service Bureaus
Industry Memberships
Alliances Home
Communities
Industry Insights Blog
Low Power Blog
Mixed-Signal Design Blog
System Design and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Quicklinks
All Blogs
All Forums
Community Search
CDN
Live!
User Conferences
Community Home
EDA Vision
Visit the EDA360 microsite
News and Events:
Newsroom
Events and Webinars
Resources:
Customer Success
Newsletters
Publications
Multimedia Center
Logos
Company Info:
Investor Relations
Executive Team
Careers
Contact Us
About Cadence Home
Home
>
Community
>
Tags
> IR drop
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.
Register
|
Membership benefits
Get email delivery of the Cadence blog (individual posts).
Industry Insights
Low Power
Mixed-Signal Design
System Design
and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Manufacturability Signoff
All Blog Categories
Popular Tags
Allegro
ARM
Custom IC Design
DAC
Digital Implementation
e
EDA360
encounter
ESL
Functional Verification
Incisive
industry insights
Logic Design
Low power
OVM
PCB
PCB design
Specman
System Design and Verification
SystemC
SystemVerilog
TLM
UVM
verification
Virtuoso
Browse All Tags
Share
Email
Social Web
*
Required Fields
Recipients email
*
(separate multiple addresses with commas)
Your name
*
Your email
*
Message
*
Send yourself a copy
Subscribe
RSS
Cadence RSS Feeds
Cadence Press Releases
System Design and Verification Blog
Functional Verification Blog
Digital Implementation Blog
Custom IC Design Blog
RF Design Blog
PCB Design Blog
IC Packaging and SiP Design Blog
Manufacturability Signoff Blog
All Blogs
System Design and Verification Forum
Functional Verification Forum
Digital Implementation Forum
Custom IC Design Forum
Custom IC SKILL Forum
Logic Design Forum
RF Design Forum
PCB Design Forum
PCB SKILL Forum
IC Packaging and SiP Design Forum
Manufacturability Signoff Forum
Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.
Contact Us
Cadence Contacts
Community Relations
Customer Support
Employment
Investor Relations
Media Relations
Training
Global Office Locator
Find Offices worldwide
»
Sales Inquiry
Request for Product information
»
Cadence Channel Partners
»
Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
*
Required Fields
First Name
*
Last Name
*
Email
*
Company / Institution
*
Comments:
*
Send Yourself A Copy
IR drop
adaptive
Aitken
Allegro
Analog
analog IP
analog/mixed-signal
ARM
ATE
ATPG
AVS
Azuro
blow up chip
broadcom
ccopt
CDN Live
CDNlive
CDNLive!
chip/package co-design
clock concurrent optimization
clock gating
clock tres synthesis
clocking
Cortex-A9
CPF
CTS
design rules
DesignCon
DFM
DFT
DFVS
Digital end-to-end flow
Digital Implementation
don't care
DRC
DVFS
Dynamic power
dynamic rail analysis
EDI 10.1
EDI system
EDP
electromigration
electro-migration
Electronic Design Processes
EM Failures
Encounter
Encounter Power System
Encounter Test
EPS
ETS
false fail
fanout
Fast SPICE
frequency
full wave
hierarchical design
In-Design Signoff
Industry Insights
LDO
low power
low-power
LVS
mixed signal
Mixed-Signal
MSV
PCB
PCB PI
PCB Signal and power integrity
PDN
Power
power analysis
Power Delivery Network
PSO
PVT
RNM
scaling
scan
scan chain
shutoff
SI analysis
signoff
Signoff Analysis
simulation
SPICE
SRAM
state retention
static timing analysis
tapeout
TeamAllegro
test mode
test power
test sequence
tester
thermal
VDD
VDD I/O
Virtuoso
Virtuoso Power System
voltage
webinar
wreal
User View: Broadcom Evaluates Clock Concurrent Optimization (CCOpt)
Clock concurrent optimization (CCOpt) is a new technology that runs clock tree synthesis (CTS) concurrently with physical optimization. It claims significant improvements in performance, power, and area - but the only way to really quantify such claims is through customer experience with real designs...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, May 23 2012
Don’t Blow Up Your Chip on the Tester!
The photo at right shows a test socket and chip destroyed by thermal runaway. Can this really happen? Yes, it can and it sometimes does, if test power is significantly greater than functional power. To get a handle on this problem I talked to Bassilios Petrakis, product marketing director for Design...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Mar 26 2012
Webinar Report: Solving Mixed-Signal Power Grid Challenges
Complex analog/mixed-signal ICs pose many power grid design and analysis challenges. Unanticipated IR drop and electromigration problems are commonplace, and they significantly impact circuit behavior. But as a recently archived webinar shows, there are a number of ways to minimize these problems, even...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Jan 11 2012
ARM Keynote: Some Inconvenient Truths About Low-Power Design
While there have been many advances in low-power IC design, it still involves tough choices and poses difficult questions, according to Rob Aitken, R&D fellow at ARM. Aitken talked about the myths and realities of low-power design in a keynote speech at the recent IEEE Electronic Design Processes...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Apr 17 2011
Tortoise Versus Hare … or How to Improve Your Time to Tapeout Using In-Design Signoff
Now that Wei Lii Tan has helped you with your New Year’s resolution to “create a chip that is so compelling …” in his previous blog , I would like to help you understand how Cadence is using our signoff qualified engines during the design implementation flow to reduce your time...
Posted to
Digital Implementation
(Weblog)
by
PeteMc
on Wed, Feb 23 2011
Team Allegro Continues Demonstration of New PDN Analysis Technology at DesignCon 2011
Today at DesignCon, drop by the Cadence booth to see TeamAllegro continue the demonstration of our new power delivery network (PDN) analysis technology for PCB design and analysis. See how during the pre-route phase of PCB design, plane shapes can be planned and optimized along with the PCB stackup....
Posted to
PCB Design
(Weblog)
by
TeamAllegro
on Wed, Feb 2 2011
Team Allegro Showing New PCB PDN Analysis Technology at DesignCon 2011
Today at DesignCon, drop by the Cadence booth to see TeamAllegro demonstrate the new power delivery network (PDN) analysis technology for PCB design and analysis. This is important because higher speed technologies such as DDR3 require lower voltages. Lower voltages provide less margin for IR drop caused...
Posted to
PCB Design
(Weblog)
by
TeamAllegro
on Tue, Feb 1 2011
Team Allegro to Boost Power of PCB PDN Solution – Sneak Peek at DesignCon 2011
The Cadence booth at DesignCon 2011 will provide visitors with a demonstration of new technology that has been developed for analysis of the power delivery network (PDN) of a printed circuit board (PCB). This new technology features enhanced static IR drop analysis, and is the foundation of a complete...
Posted to
PCB Design
(Weblog)
by
TeamAllegro
on Mon, Jan 31 2011
Digital Centric Mixed-Signal Dynamic Power Verification – Bringing It All Together
This is the final posting in a series of blogs on dynamic power management in digital-centric mixed-signal verification environments. In this post, I will talk about concepts behind digital-centric mixed-signal verification (DMSV). My previous blogs covered some of the following topics: 1. Basics of...
Posted to
Low Power
(Weblog)
by
Neyaz
on Tue, Oct 19 2010
Analog Coverage Metrics in Mixed-Signal Simulations
This posting is part of a series of blogs on dynamic power management in digital-centric mixed-signal verification environments. In this post, I will cover metrics collection from analog circuits during mixed-signal simulation. My previous blogs covered some of the following topics: 1. Basics of dynamic...
Posted to
Low Power
(Weblog)
by
Neyaz
on Tue, Oct 5 2010
Page 1 of 2 (15 items) 1
2
Next >