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IR Drop
"PCB PI"
"PCB SI"
16.5
3D viewer
adaptive
Aitken
Allegro
Allegro 16.5
Allegro PCB SI
Analog
analog IP
analog/mixed-signal
ARM
ATE
ATPG
AVS
Azuro
blow up chip
broadcom
ccopt
CDN Live
CDNlive
CDNLive!
chip/package co-design
clock concurrent optimization
clock gating
clock tres synthesis
clocking
Cortex-A9
CPF
CTS
current density
design
design rules
DesignCon
DFM
DFT
DFVS
Digital end-to-end flow
Digital Implementation
don't care
DRC
DVFS
Dynamic power
dynamic rail analysis
EDI 10.1
EDI system
EDP
electromigration
electro-migration
Electronic Design Processes
EM
EM Failures
Encounter
encounter power system
Encounter Test
EPS
ETS
false fail
fanout
Fast SPICE
five minute tutorial
frequency
full wave
Grzenia
hierarchical design
high capacity
High Speed
Industry Insights
LDO
low power
low-power
mixed signal
Mixed-Signal
MSV
PCB
PCB PI
PCB SI
PCB Signal and power integrity
PDN
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power analysis
Power Delivery Network
power integrity
PSO
PVT
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SPB16.5
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Virtuoso
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wreal
Five-Minute Tutorial: Create Encounter Power System (EPS) Power-Grid Views For Standard Cells
In today's tutorial, I'm giving you a sample EPS (Encounter Power System) script that you can use to generate power-grid views for your standard cells. Power-grid views are used during rail analysis, with IR-Drop and EM (electromigration/current density) being the two most popular analysis types...
Posted to
Digital Implementation
(Weblog)
by
Kari
on Fri, Feb 22 2013
High capacity IR analysis problems
Hi, I'm using IC6.15-64b.500.6 on openSUSE 11.4. I'm trying to carry out a high capacity analogue IR drop analysis but am running into problems. I've successfully done "regular" IR drop analyses in the past using an extracted view and a post layout simulation but haven't used...
Posted to
Custom IC Design
(Forum)
by
oojah
on Fri, Oct 26 2012
What's Good About PCB SI Static IR Drop Analysis? 16.5 Has Many New Enhancements!
In the Allegro PCB SI 16.5 release, static IR drop analysis has been integrated into PDN (power delivery network) analysis, with several new features added, such as current density display and the display of current direction. Read on for more details … Analyze Menu To invoke Static IR Drop analyze...
Posted to
PCB Design
(Weblog)
by
Jerry GenPart
on Tue, Oct 2 2012
User View: Broadcom Evaluates Clock Concurrent Optimization (CCOpt)
Clock concurrent optimization (CCOpt) is a new technology that runs clock tree synthesis (CTS) concurrently with physical optimization. It claims significant improvements in performance, power, and area - but the only way to really quantify such claims is through customer experience with real designs...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, May 23 2012
Don’t Blow Up Your Chip on the Tester!
The photo at right shows a test socket and chip destroyed by thermal runaway. Can this really happen? Yes, it can and it sometimes does, if test power is significantly greater than functional power. To get a handle on this problem I talked to Bassilios Petrakis, product marketing director for Design...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Mar 26 2012
Webinar Report: Solving Mixed-Signal Power Grid Challenges
Complex analog/mixed-signal ICs pose many power grid design and analysis challenges. Unanticipated IR drop and electromigration problems are commonplace, and they significantly impact circuit behavior. But as a recently archived webinar shows, there are a number of ways to minimize these problems, even...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Jan 11 2012
ARM Keynote: Some Inconvenient Truths About Low-Power Design
While there have been many advances in low-power IC design, it still involves tough choices and poses difficult questions, according to Rob Aitken, R&D fellow at ARM. Aitken talked about the myths and realities of low-power design in a keynote speech at the recent IEEE Electronic Design Processes...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Apr 17 2011
Tortoise Versus Hare … or How to Improve Your Time to Tapeout Using In-Design Signoff
Now that Wei Lii Tan has helped you with your New Year’s resolution to “create a chip that is so compelling …” in his previous blog , I would like to help you understand how Cadence is using our signoff qualified engines during the design implementation flow to reduce your time...
Posted to
Digital Implementation
(Weblog)
by
PeteMc
on Wed, Feb 23 2011
Team Allegro Continues Demonstration of New PDN Analysis Technology at DesignCon 2011
Today at DesignCon, drop by the Cadence booth to see TeamAllegro continue the demonstration of our new power delivery network (PDN) analysis technology for PCB design and analysis. See how during the pre-route phase of PCB design, plane shapes can be planned and optimized along with the PCB stackup....
Posted to
PCB Design
(Weblog)
by
TeamAllegro
on Wed, Feb 2 2011
Team Allegro Showing New PCB PDN Analysis Technology at DesignCon 2011
Today at DesignCon, drop by the Cadence booth to see TeamAllegro demonstrate the new power delivery network (PDN) analysis technology for PCB design and analysis. This is important because higher speed technologies such as DDR3 require lower voltages. Lower voltages provide less margin for IR drop caused...
Posted to
PCB Design
(Weblog)
by
TeamAllegro
on Tue, Feb 1 2011
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