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DAC 2013: “IP Talks!” Shows What’s New in Semiconductor IP
If you're working with semiconductor IP at any phase of the design and verification process, the IP Talks! presentations at the ChipEstimate.com booth at the upcoming Design Automation Conference (DAC 2013) will provide a great deal of useful information. Now in its 7 th year, IP Talks! includes...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, May 16 2013
EDA CEOs Reveal Thoughts About Present and Future of EDA Industry
At an EDA Consortium ( EDAC ) panel discussion March 14, 2013, top executives from Cadence, Mentor, Synopsys, ARM, and EDA startup Nimbus shared their views about a range of business and technology issues facing the EDA industry. Panelists engaged in lively discussions about topics including consolidation...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Mar 18 2013
Why Cadence Agreed to Acquire Tensilica – And How It Can Change SoC Design
On March 11, 2013, Cadence announced an agreement to acquire Tensilica, a successful provider and market leader in dataplane processing IP. By providing a more complete solution for system-on-chip (SoC) design, the acquisition will facilitate a new generation of highly differentiated, low-power, high...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Mar 17 2013
Martin Lund CDNLive Keynote: Why SoCs Need “Application Optimized” IP
Systems on chip (SoCs) are incredibly varied, extremely complex, and based on rapidly changing requirements and specifications, according to Martin Lund, senior vice president for R&D at the Cadence SoC Realization Group. At a keynote speech at the CDNLive Silicon Valley conference March 12, 2013...
Posted to
Industry Insights
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by
rgoering
on Thu, Mar 14 2013
CDNLive! 2012 Proceedings – Over 150 User Presentations on Design and Verification
A fantastic resource is available for chip and system designers -- proceedings from five of the CDNLive! Conferences held in 2012. By my count this includes over 150 user-authored presentations given at CDNLive! Silicon Valley (March 12-13), CDNLive! EMEA (May 6-8), CDNLive! Taiwan (July 11), CDNLive...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Jan 9 2013
Cadence, ARM, Samsung 14nm Test Chip – Collaboration Eases FinFET Digital Implementation
A recent test chip tapeout using the Samsung 14nm FinFET process revealed significant progress in digital implementation at this new process node. Thanks to deep collaboration and extensive R&D investments in libraries, process, and tools, the digital implementation of the test chip was successfully...
Posted to
Industry Insights
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by
rgoering
on Mon, Jan 7 2013
TSMC Forum: An Update on 20nm, 3D-IC, and 16nm FinFETs
TSMC, the world's largest semiconductor foundry, is thinking big when it comes to next-generation process technology. At the TSMC Open Innovation Platform (OIP) Ecosystem Forum Oct. 16, TSMC described reference flows for 20nm and for multi-die integration, and revealed that ARM and TSMC are working...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Oct 17 2012
Q&A: Cadence VP Martin Lund Brings User Perspective to Semiconductor IP
Martin Lund joined Cadence in early 2012 as senior vice president of R&D for the SoC Realization Group. He hasn't worked for an EDA company in the past, but 12 years at Broadcom -- most recently as senior vice president and general manager of Broadcom's Network Switching Business -- gave...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Aug 20 2012
IP Talks! Video – ARM’s John Heinlein Cites SoC Success Requirements
John Heinlein, vice president of marketing for the Physical IP division at ARM, believes that an advanced system-on-chip (SoC) design shouldn't be a "leap of faith." In a keynote speech at the IP Talks! sessions at the ChipEstimate.com booth at the Design Automation Conference (DAC 2012...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Jul 10 2012
Panel: Integrating Low-Power ARM Processors into Mixed-Signal Designs
Mixed-signal chip designs with embedded digital signal processing are becoming more and more commonplace these days. How can you bring low-power processors, such as the ARM Cortex-M0 , into such designs quickly and efficiently? A lunch panel discussion at the recent Design Automation Conference (DAC...
Posted to
Industry Insights
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by
rgoering
on Wed, Jun 20 2012
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