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Martin Lund CDNLive Keynote: Why SoCs Need “Application Optimized” IP
Systems on chip (SoCs) are incredibly varied, extremely complex, and based on rapidly changing requirements and specifications, according to Martin Lund, senior vice president for R&D at the Cadence SoC Realization Group. At a keynote speech at the CDNLive Silicon Valley conference March 12, 2013...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Mar 14 2013
Webinar Report: Easing PCIe and NVMe Functional and Performance Verification
The PCI Express (PCIe) protocol is becoming more commonplace and complex, making verification a bigger challenge than before. NVM Express (NVMe), which leverages PCIe to provide an interface to flash-based storage applications, only adds to the complexity. A July 25 EE Times webinar , now available on...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Jul 30 2012
Martin Lund on the Future of IP (Video Interview)
As SoC complexity continues to rise, more IP is being utilized, and the quality and completness expected from IP is increasing rapidly. The IP industry needs to change to meet these new expectations, or risk becomming part of the problem they are actually trying to solve. Martin Lund, Senior Vice President...
Posted to
Design IP
(Weblog)
by
Neil Hand
on Wed, Jun 13 2012
EDA CEOs Speak Out: 3D-ICs, IP Integration, Low Power, and More
What's driving the EDA industry today and where is it headed in the near future? Some high-level answers to these questions came from the EDA Consortium (EDAC) annual CEO Forecast panel Feb. 29, 2012. EDA industry leaders shared their views about 3D-ICs, SoC integration, power management, industry...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Mar 5 2012
System-Level Design and the Waves of EDA
Before January comes to an end it is time for my annual flashback and brief reflection on where we are in system-level design, and a look at how the state of today compares to the predictions we made 10 years ago. 2011 was an interesting year for system-level design. In May Cadence announced its participation...
Posted to
System Design and Verification
(Weblog)
by
fschirrmeister
on Mon, Jan 30 2012
ARM TechCon Paper: Early Architectural Planning With a Digital Implementation Flow
You might think that an IC digital implementation toolset, such as the Cadence Encounter Digital Implementation System, is only useful after RTL is developed and synthesized. But that's not necessarily the case. At the recent ARM TechCon conference, Cadence and Cisco Systems presented a flow that...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Nov 30 2011
edaForum: Evolving Devices from “All in One” to “One for All”
This week I had the pleasure to attend and to present at the 11 th annual edaForum , held in Berlin, Germany. Coming back to my hometown and presenting at this conference was a real treat, even though the traffic was much worse than I remembered, mostly because on that day the Pope visited Berlin. The...
Posted to
System Design and Verification
(Weblog)
by
fschirrmeister
on Mon, Sep 26 2011
Q&A: Methodics CEO Discusses IC Data Management and SoC Development
Cadence Connections partner Methodics is a company on the move. The company got its start with VersIC, a product that brings design data management into the Cadence Virtuoso cockpit. While VersIC continues to gain users today, Methodics has recently expanded its focus with ProjectIC, a system-on-chip...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Sep 22 2011
Video: Open-Silicon CEO Warns of “Exponential Verification Nightmare”
The biggest challenge with chip design and IP integration is verification, according to Naveed Sherwani, president and CEO of Open-Silicon - and things aren't getting easier. "I believe that unlike many other industries, we have not developed our verification system in a hierarchical manner...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Jul 17 2011
Panelists Discuss Solutions to SoC IP Integration Challenges
Semiconductor intellectual property (IP) reuse makes system-on-chip (SoC) design possible, but complex SoCs pose some really tough IP integration challenges. Panelists at the May 12 EE Times System on Chip "Virtual Event" answered five questions posed by moderator Mike Demler, technical editor...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, May 15 2011
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