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INCISIVE
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Launch Time – Udacity CS348 Functional Hardware Verification Hits the Web Today, March 12, 2013
Coinciding with the first day of CDNLive! Silicon Valley, our Udacity MOOCs course on Functional Hardware Verification will go live today! Developing this course has been a very rewarding experience and we are happy this day has finally come. Last week we gave you a sneak preview of the interactivity...
Posted to
Functional Verification
(Weblog)
by
Axel Scherer
on Tue, Mar 12 2013
System to Silicon Verification – CDNLive Gives a Reality Check on How Hardware and Software Meet
Ever since switching from being a hardware/software chip developer to being an enabler with tools in EDA and embedded software, I was part of a team working towards methodologies and tools to improve the interaction of hardware and software. In December last year -- 15 years in -- I summarized a great...
Posted to
System Design and Verification
(Weblog)
by
fschirrmeister
on Fri, Mar 8 2013
Engineering Fix
Hi I have been given an Engineering fix for a problem in formal tool. The IT suppor has installed it but I am not sure how to use it. Usually the tool is used by seting SOCV_KIT_HOME and sourcing env.csh But I am not finding any such file at the folder kits/VerificationKit I will be thankful if someone...
Posted to
Functional Verification
(Forum)
by
Avni
on Mon, Mar 4 2013
"Smart Devices" and How They Affect Your Mixed-Signal SOC Verification
We are seeing a huge trend -- the mobile revolution is changing the way we go about our everyday lives. Gone are the days where the term 'Internet' was associated with a PC or Mac. The smartphone revolution has changed how the data is consumed and used by consumers and businesses. For example...
Posted to
Mixed-Signal Design
(Weblog)
by
Sathish Bala
on Mon, Feb 25 2013
Whitepaper Review: Improving Gate-Level Simulation Performance
As I wrote in a January 2013 blog post , a recent Cadence customer survey confirmed that gate-level simulation usage is increasing, and that it can potentially take up to one-third of the simulation time and over half the debugging time. Since gate-level simulation is much slower than RTL simulation...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Feb 18 2013
Why C-to-Silicon Compiler HLS has Supported IEEE 1666-2011 SystemC All Along
Recently one of our competitors issued a press release claiming to be the first high-level synthesis (HLS) vendor to support IEEE 1666 TM -2011 SystemC. Specifically mentioned was newly-added support for asynchronous resets in SC_THREADs. Congratulations to them on supporting this standard. You are probably...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Thu, Feb 14 2013
IBM and Cadence Collaboration Improves Verification Productivity
Technology leaders like IBM continuously seek opportunities to improve productivity because they recognize that verification is a significant part of the overall SoC development cycle. Through collaboration, IBM and Cadence identify, refine, and deploy verification technologies and methodologies to improve...
Posted to
Functional Verification
(Weblog)
by
Adam Sherilog
on Wed, Feb 13 2013
DVCon 2013 for Formal and ABV Users
At the upcoming DVCon (in San Jose, CA February 25-28) , Cadence will cover all aspects of our verification technologies and methodologies (full list of Cadence-sponsored events is here ). However, Team Verify would like to alert users of Cadence Incisive formal and multi-engine tools, apps, and assertion...
Posted to
Functional Verification
(Weblog)
by
TeamVerify
on Mon, Feb 11 2013
Improve Debug Productivity - SimVision Video Series on YouTube
Most verification customers claim that they are spending over 50% of their verification effort in debug. If so, you should check out these latest SimVision debug videos since you will quickly see how SimVision can enable you to be much more productive in less than an hour after viewing the videos. Take...
Posted to
Functional Verification
(Weblog)
by
Karnane
on Tue, Feb 5 2013
Specman: An Assumed Generation Issue and its Real Root Cause
Random generation is always a complex task, and differences in results are usually very hard to debug. Besides, generation misbehavior always rings many bells in R&D :-) A customer reported a random stability issue, explaining that the generator (IntelliGen) generated different values with the same...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Mon, Jan 21 2013
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