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INCISIVE,Simulation
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Incisive Debug Analyzer is a Finalist for EETimes and EDN ACE Software Product of the Year
Great news.... Incisive Debug Analyzer (IDA) is one of five finalists for the EETimes/EDN Annual Creativity in Electronics (ACE) Awards in the Software Product of the Year category. In addition to IDA, Lip-Bu Tan and Cadence are also finalists for ACE Executive of the Year and Company of the Year, respectively...
Posted to
Functional Verification
(Weblog)
by
Karnane
on Mon, Mar 25 2013
Whitepaper Review: Improving Gate-Level Simulation Performance
As I wrote in a January 2013 blog post , a recent Cadence customer survey confirmed that gate-level simulation usage is increasing, and that it can potentially take up to one-third of the simulation time and over half the debugging time. Since gate-level simulation is much slower than RTL simulation...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Feb 18 2013
Functional Verification Survey -- Why Gate-Level Simulation is Increasing
In a recent webinar on increasing functional verification performance, the point was made that gate-level simulation usage is increasing. Wait a minute, I thought - haven't we spent the last two decades talking about raising the abstraction level for design and verification? While some IC verification...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Jan 16 2013
Webinar Report: Speeding RTL and Gate-Level Simulation
Every verification team wants faster functional verification performance. Fortunately, there are many ways to achieve that. A recently archived Cadence webinar illustrates a number of techniques for speeding both RTL and gate-level simulation, including "out of the box" improvements to the...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Dec 13 2012
Archived Webinar: New Technology Attacks the Verification Debug Bottleneck
Verification debug hasn't exactly been a hotbed of technology innovation, even though verification teams report that debugging can consume more than 50% of the overall verification effort. A recently archived Cadence webinar reviews common debug challenges and shows how the new Incisive Debug Analyzer...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Nov 29 2012
Recorded Webinar: Using Metric-Driven Verification and Formal Together For Higher Productivity
[Preface: the upcoming " Club Formal " on October 17 here at the Cadence San Jose campus will also touch on this topic - please join us! ] While it's now common knowledge that there are many benefits to using simulation technology within a metric-driven verification (MDV) flow , as it turns...
Posted to
Functional Verification
(Weblog)
by
TeamVerify
on Wed, Oct 10 2012
The Cowbell Rings On – We Have Completed the “UVM SystemVerilog Basics” Videos in Chinese
In July we released 12 videos of the UVM SystemVerilog Basics series with Chinese audio . Now we are completing the set and releasing the remaining 13 videos. Interface UVC Environment Virtual Sequencer - Sequence Module UVC Scoreboard DUT Functional Coverage Testbench Test Configuration Factory Phases...
Posted to
Functional Verification
(Weblog)
by
Axel Scherer
on Tue, Sep 4 2012
Designer View – Using Metric-Driven Verification for Mixed-Signal IP
Can digital verification techniques such as verification planning, coverage metrics, and assertion checking be applied to the analog/mixed-signal world? Yes, according to Pierluigi Daglio, analog verification engineer at STMicroelectronics. In a recorded presentation at the Cadence web site, he shows...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Aug 29 2012
A “Reflection” on Chip-Level Debugging with Specman/e and SimVision
Last week, a favorite customer of mine called me in a panic, just days from tape-out of a large multimedia SoC. After a minor change in their RTL code their Specman testbench started crashing, even though the e code wasn't changed. Could I help? Knowing that this customer compiles their e code, and...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Wed, Aug 15 2012
Webinar: Speeding UVM SystemVerilog Simulation With Software Engineering Techniques
You may be a software engineer and not even know it. If you develop IC verification environments, the way you write and optimize code has a tremendous impact on simulation performance. A recently archived Cadence webinar provided a number of practical tips to help you analyze and optimize Universal Verification...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Aug 8 2012
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