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INCISIVE,OVM ML,SystemVerilog

  • "We Want UVM 1.0! When Do We Want it? Now!"

    Short of holding signs and yelling slogans, the 12 customers I visited in the past week all declared this mantra. All are planning to move to UVM 1.0 with all of them requiring the phasing and register package capabilities, but only one also requiring TLM2 support, primarily for accessing SystemC models...
    Posted to Functional Verification (Weblog) by Adam Sherilog on Thu, Oct 7 2010
  • DVCon 2010 For The Specmaniac

    At next week's DVCon in San Jose, CA, Cadence will cover all aspects of our verification technologies and methodologies ( full list of Cadence-sponsored activities is posted here ). Of course, Team Specman is here help Specmaniacs discover the many activities that will feature Specman and e language...
    Posted to Functional Verification (Weblog) by teamspecman on Mon, Feb 15 2010
  • Adam’s Verification Top 10 In '10

    I love top 10 lists. Not so much for the drama of the count-down, but for arguments that inevitably fall out of any prioritization. So here is my verification top 10 in '10, let the rants begin! 10. VHDL 1076-2009 Support . Huh? How did this get here? Given the breadth of IES (Incisive Enterprise...
    Posted to Functional Verification (Weblog) by Adam Sherilog on Tue, Dec 29 2009
  • CDNLive San Jose 2009 for the Specmaniac

    Even sooner than the EU ClubTs is CDNLive San Jose 2009 , where this year the event is a "hybrid" format of in-person workshops and on-line webinars. As with past CDNLive's, the agenda spans the entire Cadence product line, subdivided into tracks for the major segments of the design &...
    Posted to Functional Verification (Weblog) by teamspecman on Wed, Sep 30 2009
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