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IES

What Does Silicon Realization Mean for Verification Engineers?

Last May , I posed a question about what EDA360 means for verification engineers. Yesterday we made an announcement about verification for Silicon Realization that is a big deal. We are delivering a lot of new technology with immediate and high value to verification engineers everywhere. My colleagues...

Posted to Functional Verification (Weblog) by tomacadence on Tue, Jan 11 2011
Infinite Playbook for the Verification Superbowl

Its 4th and long, you're down by six, the clock is running out, and you are wary of a bug-blitz. What play do you call? With new approach defined by Silicon Realization, the updated Incisive Enterprise Simulator provides the new capabilities to finsh your drive, route the bugs, and win the verification...

Posted to Functional Verification (Weblog) by Team genIES on Mon, Jan 10 2011
Cadence Low-power Verification: Tear Down These Walls

You've been building chips for years and the growing complexity means you just can't tolerate simple tool-to-tool flows and group-to-group barriers any more. SystemC and RTL in the same low-power simulation? Got it. Mixed-signal? Yep. Every team with fingers in the power intent? For sure. Siicon...

Posted to Low Power (Weblog) by Adam Sherilog on Tue, Nov 2 2010
"We Want UVM 1.0! When Do We Want it? Now!"

Short of holding signs and yelling slogans, the 12 customers I visited in the past week all declared this mantra. All are planning to move to UVM 1.0 with all of them requiring the phasing and register package capabilities, but only one also requiring TLM2 support, primarily for accessing SystemC models...

Posted to Functional Verification (Weblog) by Adam Sherilog on Thu, Oct 7 2010
e Templates: A Nifty Way To Create Reusable Code

Hi All, An e template (known as a parameterized type in other programming languages) is a feature that has been around for several releases and can be a great way of creating re-usable code. Templates can be used anywhere a user would like to create a single re-useable object that might operate on different...

Posted to Functional Verification (Weblog) by teamspecman on Tue, Aug 10 2010
DAC Cabbie Taught Me All I Need to Know About Verification

Confidence from competence. Measurement through metrics. Sell without selling. These are the pearls I learned from my cab driver on the way home from DAC. Aside from the core truths they convey, they clearly define the top three verification items I saw at 47th DAC in Anaheim this year. Topping my list...

Posted to Functional Verification (Weblog) by Adam Sherilog on Mon, Jun 21 2010
Harris-Cadence-Mathworks-Xilinx Success Cuts Verification Time 85%

More and more often it takes a village to achieve verification success. As reported recently by MathWorks, Harris pulled together technology and support from Cadence, MathWorks, and Xilinx to cut their verification time by more than 85% and achieve a defect-free FPGA implementation. “EDA Simulator Link...

Posted to Functional Verification (Weblog) by Adam Sherilog on Thu, Apr 29 2010
DVCon: Showcasing The Cadence Passion For Verification Excellence

Yeah, I know I'm a marketing guy but I really like this stuff! For sure, we are going tech-deep in our tutorials and papers, but we are also setting vision and direction for verification in our keynote presentation. For all of the details, visit our DVCon events page . Highlighted below are two of...

Posted to Functional Verification (Weblog) by Adam Sherilog on Mon, Feb 22 2010
Re: SV-201x Listening Campaign

Hello Shalom, Thanks for this post. We also encourage customers to make their views known. This type of group participation certainly helps us prioritize our engineering work. =Adam Sh e rilog

Posted to Functional Verification (Forum) by Adam Sherilog on Wed, Feb 17 2010
Low-Power Verification With SystemC - The Great Unknown

Design teams have used C/C++/SystemC reference models for many years and the trend is growing with SystemC synthesis. At the same time, many teams are adding power-aware structures to their designs and trying to simulate. So what happens when the models encounter unknowns propagated from shutdown blocks...

Posted to Functional Verification (Weblog) by Team genIES on Thu, Jan 28 2010

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IES

What Does Silicon Realization Mean for Verification Engineers?

Infinite Playbook for the Verification Superbowl

Cadence Low-power Verification: Tear Down These Walls

"We Want UVM 1.0! When Do We Want it? Now!"

e Templates: A Nifty Way To Create Reusable Code

DAC Cabbie Taught Me All I Need to Know About Verification

Harris-Cadence-Mathworks-Xilinx Success Cuts Verification Time 85%

DVCon: Showcasing The Cadence Passion For Verification Excellence

Re: SV-201x Listening Campaign

Low-Power Verification With SystemC - The Great Unknown