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IES

UVM: "Everything that Can be Invented Has Been Invented" Not True!

Much like Charles Duell's famous 1899 quote**, the notion that the Universal Verification Methodology ( UVM ) is the be-all and end-all of verification methodology is an urban legend. The new Advanced Verification Topics book dispells this myth with five topics that describe methodology layers that...

Posted to Functional Verification (Weblog) by Adam Sherilog on Thu, Jan 26 2012
Holiday Idea #1: Give the Gift of UVM Knowledge

Your favorite verification engineer has been good all year. Thousands of tests run. Nights and weekends of debug. So how do reward her? Why, with UVM Training , of course! Cadence experts have trained hundreds of engineers on OVM and UVM. These trainers have deep knowledge in both the methodology and...

Posted to Functional Verification (Weblog) by Adam Sherilog on Tue, Dec 6 2011
Update to the OVM Register Package

OVM users have something new to give thanks for this holiday season -- an update to the OVM Register Package (new link!!). This package is used by novice and advanced users and embodies years of experience gathered through hundreds of SystemVerilog projects. The Cadence genIES team has been remiss since...

Posted to Functional Verification (Weblog) by Team genIES on Tue, Nov 29 2011
Come See How to Connect SystemVerilog and SystemC Using UVM

All pun-tastic references aside, connecting SystemVerilog and SystemC is becoming a commonplace request. In most cases, the request is to do this using UVM as the testbench methodology. One of our resident technical experts, Phu Huynh, will lead a webinar on this subject on October 20. Cadence pioneered...

Posted to Functional Verification (Weblog) by Adam Sherilog on Tue, Oct 18 2011
Automating UVM to Tackle Insidious HW/SW Bugs

You've just sat through a 2-hour program review. The 30 minutes you spent describing your sparkling new UVM verification environment were electrifying. Of course, the hardware and software reviews were boring. Blah, blah, blah about design trade-offs with some buried references to register APIs....

Posted to Functional Verification (Weblog) by Adam Sherilog on Mon, Oct 10 2011
Low-power Keeps Gate-Level Simulation Forever Young

Ann Mutschler blogged in the Low-Power Engineering Community that gate-level simulation is coming back, driven in part by low-power verification needs. “In a small sense, what’s old is new” may actually be the biggest understatement in her blog. Ann attributes the observation to Cadence’s...

Posted to Low Power (Weblog) by Adam Sherilog on Thu, Sep 8 2011
OVM 2.1.2 -- Getting You Ready for UVM

Talk about stability -- OVM 2.1.1 has had 18 months as the core of Accellera's UVM and accumulated only 13 bugs. Not too shabby! With the OVM community preparing to migrate, Cadence and Mentor have posted a bug-fix update -- OVM 2.1.2 -- to OVMWorld to help you get ready to move to the UVM. As you...

Posted to Functional Verification (Weblog) by Adam Sherilog on Tue, May 31 2011
2011 CDNLive EMEA Highlights and Image Gallery: An EDA360 Spring Festival of Deliverables

Last week teammate Adam Sherer and I had the honor of representing the Incisive functional verification platform at the annual CDNLive for Europe, the Middle East and Africa (EMEA) in Munich, Germany. Among our tasks was to deliver the annual verification roadmap update; support numerous techtorials...

Posted to Functional Verification (Weblog) by jvh3 on Tue, May 10 2011
Being a Part of Something Truly Remarkable - UVM

For just over two years I have had the honor of playing a role in a dramatic example of EDA360 in action -- the creation of the Accellera UVM standard 1.0. I could not be more proud! Many will measure UVM 1.0 in terms of features, but it is much more than that. It represents a different way of conducting...

Posted to Functional Verification (Weblog) by Adam Sherilog on Fri, Feb 18 2011
Achieve the Next Level of Verification Productivity with Specman Advanced Option

Advanced verification customers are seeing their verification environments getting more and more complex requiring millions of lines of code spread across hundreds, even thousands of files that are re-used from Block --> SoC --> System level. Today's design under test (DUT) can be extremely...

Posted to Functional Verification (Weblog) by teamspecman on Tue, Jan 18 2011

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IES

UVM: "Everything that Can be Invented Has Been Invented" Not True!

Holiday Idea #1: Give the Gift of UVM Knowledge

Update to the OVM Register Package

Come See How to Connect SystemVerilog and SystemC Using UVM

Automating UVM to Tackle Insidious HW/SW Bugs

Low-power Keeps Gate-Level Simulation Forever Young

OVM 2.1.2 -- Getting You Ready for UVM

2011 CDNLive EMEA Highlights and Image Gallery: An EDA360 Spring Festival of Deliverables

Being a Part of Something Truly Remarkable - UVM

Achieve the Next Level of Verification Productivity with Specman Advanced Option