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IES

Mode Support for SimVision “Stop Simulation” Button

Prior to Incisive Enterprise Simulator (IES) 12.1, clicking the SimVision "Stop Simulation" button would stop the simulation both in an HDL context and in a Specman context if Specman was present in the simulation. To provide better flexibility in the exact place where you want to pause, the...

Posted to Functional Verification (Weblog) by teamspecman on Wed, May 8 2013
New Incisive Low-Power Verification for CPF and IEEE 1801 / UPF

On May 7, 2013 Cadence announced a 30% productivity gain in the June 2013 Incisive Enterprise Simulator 13.1 release . Advanced debug visualization, faster turn-around time, and the extension of eight years of low-power verification innovation to IEEE 1801/UPF are the key capabilities in the release...

Posted to Low Power (Weblog) by Adam Sherilog on Tue, May 7 2013
Bidirectional has() and count() List Pseudo-Methods

Hi. As of the 11.1 release, the list.has() and list.count() list pseudo-methods can be treated as bidirectional constraint operators. In 11.1, list.has() and list.count() are solved unidirectionally by default. To ensure that these pseudo-methods are solved as bidirectional expressions, set the config...

Posted to Functional Verification (Forum) by IonutC on Tue, Mar 5 2013
Planning to Go to DVCon 2013 Next Week? If So, Don't Miss the Debug Tutorial Feb. 28th!

TUTORIAL : Fast Track Your UVM Debug Productivity with Simulation and Acceleration Session: 5T on Thursday, Feb. 28 th from 8:30AM - 12:00PM For more details on the debug tutorial, click here This debug tutorial will highlight how customers can reduce their debug turnaround time by employing the most...

Posted to Functional Verification (Weblog) by Karnane on Wed, Feb 20 2013
IBM and Cadence Collaboration Improves Verification Productivity

Technology leaders like IBM continuously seek opportunities to improve productivity because they recognize that verification is a significant part of the overall SoC development cycle. Through collaboration, IBM and Cadence identify, refine, and deploy verification technologies and methodologies to improve...

Posted to Functional Verification (Weblog) by Adam Sherilog on Wed, Feb 13 2013
Improve Debug Productivity - SimVision Video Series on YouTube

Most verification customers claim that they are spending over 50% of their verification effort in debug. If so, you should check out these latest SimVision debug videos since you will quickly see how SimVision can enable you to be much more productive in less than an hour after viewing the videos. Take...

Posted to Functional Verification (Weblog) by Karnane on Tue, Feb 5 2013
Your First Low-power Verification Project - Webinar

So your team just specified its first design with power management circuits. The designers are telling you, its just a few power shut-off domains defined by CPF or UPF. The verification should be easy-peasy right? Wrong. Each domain has complete controls, isolation, and retention. As a verification engineer...

Posted to Low Power (Weblog) by Adam Sherilog on Thu, Oct 11 2012
UVM SystemVerilog in a Multi-Language SoC World: UVM-ML Webinar

Every SoC project uses multiple languages. Even if the design itself is purely Verilog RTL, it's likely that you have some PLI-based stimulus. In many cases there are multiple languages in use due to multiple suppliers, globalized teams, multiple abstractions, and more. Integrating e , SystemVerilog...

Posted to Functional Verification (Weblog) by Adam Sherilog on Thu, Oct 11 2012
The Cowbell Rings On – We Have Completed the “UVM SystemVerilog Basics” Videos in Chinese

In July we released 12 videos of the UVM SystemVerilog Basics series with Chinese audio . Now we are completing the set and releasing the remaining 13 videos. Interface UVC Environment Virtual Sequencer - Sequence Module UVC Scoreboard DUT Functional Coverage Testbench Test Configuration Factory Phases...

Posted to Functional Verification (Weblog) by Axel Scherer on Tue, Sep 4 2012
Constrained Random Test Generation In e [IEEE 1647], Ernie * Duracell ≈ Infinity Minus

Ernie & Duracell "I feel great" - long pause - "I feel great, I feel great". 6 weeks later: "I feel great, I feel great, I feel great" - pause - "I feel great". I hear this sound coming out of my son's room. What is going on in my house? Is there such a...

Posted to Functional Verification (Weblog) by Axel Scherer on Wed, Aug 1 2012

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IES

Mode Support for SimVision “Stop Simulation” Button

New Incisive Low-Power Verification for CPF and IEEE 1801 / UPF

Bidirectional has() and count() List Pseudo-Methods

Planning to Go to DVCon 2013 Next Week? If So, Don't Miss the Debug Tutorial Feb. 28th!

IBM and Cadence Collaboration Improves Verification Productivity

Improve Debug Productivity - SimVision Video Series on YouTube

Your First Low-power Verification Project - Webinar

UVM SystemVerilog in a Multi-Language SoC World: UVM-ML Webinar

The Cowbell Rings On – We Have Completed the “UVM SystemVerilog Basics” Videos in Chinese

Constrained Random Test Generation In e [IEEE 1647], Ernie * Duracell ≈ Infinity Minus