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IES,SystemVerilog

Get Started on UVM-e with Free Introductory Video Tutorials

One of the many requests that we get from Specman/ e customers is that they would like some basic e tutorials. So, as a first step, Axel Scherer has recently posted 24, very short, byte sized UVM- e basic tutorials . Check them out. These e -based videos are targeted for design and verification engineers...

Posted to Functional Verification (Weblog) by teamspecman on Thu, May 24 2012
UVM e (IEEE 1647) Video Series Features the Return of the Cowbell!

A significant number of readers of my previous post on this topic were not aware of the Saturday Night Live cowbell skit. This took me quite by surprise! The only prescription for this problem is that I pledge to continue to play the cultural ambassador and will introduce more vital trivia! However,...

Posted to Functional Verification (Weblog) by Axel Scherer on Mon, May 21 2012
UVM SystemVerilog Video Series Brings Verification World "More Cowbell!"

To quote an American pop culture catchphrase made famous by Saturday Night Live character Bruce Dickison , "I gotta have more cowbell !" In the world of functional verification this translates to "more collateral!" Thererfore, we have released a set of byte-size videos about the basics...

Posted to Functional Verification (Weblog) by Axel Scherer on Thu, May 3 2012
Gentlemen, Start Your Simulation Engines

As we outlined in our recent performance white paper , every verification team has the need for higher performance simulation. Of course, you can expect on-going innovation from Cadence R&D, but there are some things you can do to get more from your engine at any time. The February 23, 2012 webinar...

Posted to Functional Verification (Weblog) by Adam Sherilog on Wed, Feb 22 2012
UVM: "Everything that Can be Invented Has Been Invented" Not True!

Much like Charles Duell's famous 1899 quote**, the notion that the Universal Verification Methodology ( UVM ) is the be-all and end-all of verification methodology is an urban legend. The new Advanced Verification Topics book dispells this myth with five topics that describe methodology layers that...

Posted to Functional Verification (Weblog) by Adam Sherilog on Thu, Jan 26 2012
Come See How to Connect SystemVerilog and SystemC Using UVM

All pun-tastic references aside, connecting SystemVerilog and SystemC is becoming a commonplace request. In most cases, the request is to do this using UVM as the testbench methodology. One of our resident technical experts, Phu Huynh, will lead a webinar on this subject on October 20. Cadence pioneered...

Posted to Functional Verification (Weblog) by Adam Sherilog on Tue, Oct 18 2011
Automating UVM to Tackle Insidious HW/SW Bugs

You've just sat through a 2-hour program review. The 30 minutes you spent describing your sparkling new UVM verification environment were electrifying. Of course, the hardware and software reviews were boring. Blah, blah, blah about design trade-offs with some buried references to register APIs....

Posted to Functional Verification (Weblog) by Adam Sherilog on Mon, Oct 10 2011
OVM 2.1.2 -- Getting You Ready for UVM

Talk about stability -- OVM 2.1.1 has had 18 months as the core of Accellera's UVM and accumulated only 13 bugs. Not too shabby! With the OVM community preparing to migrate, Cadence and Mentor have posted a bug-fix update -- OVM 2.1.2 -- to OVMWorld to help you get ready to move to the UVM. As you...

Posted to Functional Verification (Weblog) by Adam Sherilog on Tue, May 31 2011
Infinite Playbook for the Verification Superbowl

Its 4th and long, you're down by six, the clock is running out, and you are wary of a bug-blitz. What play do you call? With new approach defined by Silicon Realization, the updated Incisive Enterprise Simulator provides the new capabilities to finsh your drive, route the bugs, and win the verification...

Posted to Functional Verification (Weblog) by Team genIES on Mon, Jan 10 2011
"We Want UVM 1.0! When Do We Want it? Now!"

Short of holding signs and yelling slogans, the 12 customers I visited in the past week all declared this mantra. All are planning to move to UVM 1.0 with all of them requiring the phasing and register package capabilities, but only one also requiring TLM2 support, primarily for accessing SystemC models...

Posted to Functional Verification (Weblog) by Adam Sherilog on Thu, Oct 7 2010

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IES,SystemVerilog

Get Started on UVM-e with Free Introductory Video Tutorials

UVM e (IEEE 1647) Video Series Features the Return of the Cowbell!

UVM SystemVerilog Video Series Brings Verification World "More Cowbell!"

Gentlemen, Start Your Simulation Engines

UVM: "Everything that Can be Invented Has Been Invented" Not True!

Come See How to Connect SystemVerilog and SystemC Using UVM

Automating UVM to Tackle Insidious HW/SW Bugs

OVM 2.1.2 -- Getting You Ready for UVM

Infinite Playbook for the Verification Superbowl

"We Want UVM 1.0! When Do We Want it? Now!"