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Send Yourself A Copy
IES,IES-XL,Incisive Enterprise Simulator (IES)
: Functional Verification
20nm
Adam Sherer
Adaptive Voltage Scaling
AF
AMS
AOP
Aspect Oriented Programming
assertion-based verification
Avi Behar
AVS
bug
Cadence
CDNLive
ClubT
coverage driven verification
coverage driven verification (CDV)
Coverage-Driven Verification
debug
Debug Performance
debug tutorial
debugging
DVcon
e
EDA360
EMEA
Enterprise Manager
Enterprise Planner
eRM
esl tlm synthesis rtl dac estimation planning
festival
Funcional Verification
Functional Verificatioa
Functional Verification
funtional verification
gate level
gate-level
hvl
IEEE 1647
IEV
IFV
Incisive
Incisive Debug Analyzer
Incisive Enterprise Simulator
Incisive performance
innovation
IntelliGen
Joe Hupcey III
Low Power
Low-power
macros
metric driven verification (MDV)
Mixed Signal Verification
Mixed-Signal
multi-core
multi-language
Object Oriented Programming
OOP
Open Verification Methodology
OVM e
OVM-e
OVMWorld
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RTL design
sequences
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Planning to Go to DVCon 2013 Next Week? If So, Don't Miss the Debug Tutorial Feb. 28th!
TUTORIAL : Fast Track Your UVM Debug Productivity with Simulation and Acceleration Session: 5T on Thursday, Feb. 28 th from 8:30AM - 12:00PM For more details on the debug tutorial, click here This debug tutorial will highlight how customers can reduce their debug turnaround time by employing the most...
Posted to
Functional Verification
(Weblog)
by
Karnane
on Wed, Feb 20 2013
Improve Debug Productivity - SimVision Video Series on YouTube
Most verification customers claim that they are spending over 50% of their verification effort in debug. If so, you should check out these latest SimVision debug videos since you will quickly see how SimVision can enable you to be much more productive in less than an hour after viewing the videos. Take...
Posted to
Functional Verification
(Weblog)
by
Karnane
on Tue, Feb 5 2013
Gentlemen, Start Your Simulation Engines
As we outlined in our recent performance white paper , every verification team has the need for higher performance simulation. Of course, you can expect on-going innovation from Cadence R&D, but there are some things you can do to get more from your engine at any time. The February 23, 2012 webinar...
Posted to
Functional Verification
(Weblog)
by
Adam Sherilog
on Wed, Feb 22 2012
Incisive Performance Scales to Meet Advanced Node SoC Verification Requirements
Its’ all about RTL simulation. I mean gates. I mean turn-around-time. Project-level productivity. Mixed-signal. Low-power. UVM. And. And. And. … And the reality is that advanced node SoCs are so complex that it is truly about all of these. Our new white paper details a systematic approach...
Posted to
Functional Verification
(Weblog)
by
Adam Sherilog
on Mon, Jan 30 2012
2011 CDNLive EMEA Highlights and Image Gallery: An EDA360 Spring Festival of Deliverables
Last week teammate Adam Sherer and I had the honor of representing the Incisive functional verification platform at the annual CDNLive for Europe, the Middle East and Africa (EMEA) in Munich, Germany. Among our tasks was to deliver the annual verification roadmap update; support numerous techtorials...
Posted to
Functional Verification
(Weblog)
by
jvh3
on Tue, May 10 2011
e Templates: A Nifty Way To Create Reusable Code
Hi All, An e template (known as a parameterized type in other programming languages) is a feature that has been around for several releases and can be a great way of creating re-usable code. Templates can be used anywhere a user would like to create a single re-useable object that might operate on different...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Tue, Aug 10 2010
Demo: New Signal Tracing Capability in Incisive Enterprise Simulator
One of the great things about working here at Cadence is having the opportunity to test and preview new features and functionality before public release. The newly released 9.2 version of Incisive Enterprise Simulator contains a new streamlined signal tracing function in SimVision. I thought you might...
Posted to
Functional Verification
(Weblog)
by
hilker
on Wed, Oct 21 2009
Demo: New Simulation Comparison Utility in Incisive Enterprise Simulator
When I first hired on as an AE at Cadence (eighteen years ago!), I realized how many great features were available in the software which I did not know about as a designer. So much of my time was spent on design and verification, there was little time to explore all the capabilities of the software....
Posted to
Functional Verification
(Weblog)
by
hilker
on Tue, Jun 30 2009
Create a Sine Wave Generator Using SystemVerilog
Two capabilities in SystemVerilog allow for the creation of a module that can produce a sine wave as an output: the ability to pass real values through port connections and DPI. Obviously, to produce a sine wave, you need access to the sin function. This is where DPI is handy to add the math functions...
Posted to
Functional Verification
(Weblog)
by
tpylant
on Tue, Jun 30 2009
Tips on Using “vhdlsync” With e+Mixed HDL Simulation
[ Team Specman welcomes Principal Support Application Engineer Avi Farjoun to share some important tips on the famous “vhdlsync” switch] As users with mixed VHDL and Verilog environments know, even in this day & age mixed HDL simulation cycle semantics are not very well defined. Even...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Thu, Jun 11 2009
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