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IES,CPF,IEEE 1801

  • New Incisive Low-Power Verification for CPF and IEEE 1801 / UPF

    On May 7, 2013 Cadence announced a 30% productivity gain in the June 2013 Incisive Enterprise Simulator 13.1 release . Advanced debug visualization, faster turn-around time, and the extension of eight years of low-power verification innovation to IEEE 1801/UPF are the key capabilities in the release...
    Posted to Low Power (Weblog) by Adam Sherilog on Tue, May 7 2013
  • Your First Low-power Verification Project - Webinar

    So your team just specified its first design with power management circuits. The designers are telling you, its just a few power shut-off domains defined by CPF or UPF. The verification should be easy-peasy right? Wrong. Each domain has complete controls, isolation, and retention. As a verification engineer...
    Posted to Low Power (Weblog) by Adam Sherilog on Thu, Oct 11 2012
  • Low-power Keeps Gate-Level Simulation Forever Young

    Ann Mutschler blogged in the Low-Power Engineering Community that gate-level simulation is coming back, driven in part by low-power verification needs. “In a small sense, what’s old is new” may actually be the biggest understatement in her blog. Ann attributes the observation to Cadence’s...
    Posted to Low Power (Weblog) by Adam Sherilog on Thu, Sep 8 2011
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