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Inside Cadence: Training for EDA360

Over the past few weeks all of Cadence's Verification and Systems Solutions Applications Engineers (AEs), Services Engineers, and many Customer Support staff, have been brought together for detailed methodology and product training. The objectives of this ambitious undertaking are to bring their...

Posted to Functional Verification (Weblog) by jvh3 on Thu, May 6 2010
Informative Tweets on WHEN Inheritance

Earlier today a lively and very instructive thread on the relative virtues of WHEN Inheritance developed on Twitter between @pmarriott (a D&V consultant in Montreal, Canada) , @yaron_think_ver (a verification consultant based in Israel) , and @teamspecman. Because this exchange was very technical...

Posted to Functional Verification (Weblog) by teamspecman on Tue, May 4 2010
When Less Is More, Part 3: Is e code really “infinitely” more compact than SystemVerilog?

Building on the packet generation example of part 1 , and the coverage examples of part 2 that compare the ratio of lines e code to lines of SystemVerilog for a given task, in this post I’m going to show you how to “divide by 0” and leverage e capabilities that simply don’t exist in SystemVerilog, technically...

Posted to Functional Verification (Weblog) by teamspecman on Wed, Apr 21 2010
Built-in Message Logging – Part 1 of 2

[Team Specman welcomes guest blogger Michael Avery, from our Services Group in the UK] Messaging is important for two main reasons: It is essential for debugging It can greatly impact simulation performance This is why Specman has a messaging infrastructure built-in to provide an easy to use, scalable...

Posted to Functional Verification (Weblog) by teamspecman on Thu, Mar 11 2010
Cadence Exec: Why Cadence is Comitted to e/Specman

In case you or your management are wondering about Cadence's commitment to supporting the e language and/or Specman technology, allow us to direct your attention to this interview of Cadence Verification VP Mitch Weaver (who never worked for Verisity, BTW) by industry analyst Richard Goering. As...

Posted to Functional Verification (Weblog) by teamspecman on Tue, Feb 16 2010
DVCon 2010 For The Specmaniac

At next week's DVCon in San Jose, CA, Cadence will cover all aspects of our verification technologies and methodologies ( full list of Cadence-sponsored activities is posted here ). Of course, Team Specman is here help Specmaniacs discover the many activities that will feature Specman and e language...

Posted to Functional Verification (Weblog) by teamspecman on Mon, Feb 15 2010
Beyond Coverage: Adding Arbitrary Metrics To Your Metric-Driven flow

The most common metrics used in current metric driven verification (MDV) flows are various forms of code coverage (block, FSM, toggle etc.), assertion coverage, and functional coverage. As many of you know, all of these can be collected into Enterprise Manager for individual analysis, merged together...

Posted to Functional Verification (Weblog) by teamspecman on Wed, Feb 10 2010
Tech Tip: Easy Way To Re-Run Using The Same Seed

[Team Specman welcomes back Application Engineer Hilmar Van Der Kooij as this week’s guest blogger] Often we want to re-run a simulation with the exact same random seed that was used in the previous one. Unfortunately far too many people (ok, maybe just me) have used little scraps of paper or sticky...

Posted to Functional Verification (Weblog) by teamspecman on Fri, Feb 5 2010
Tech Tip: Waving Specman Objects in SimVision

Did you know that you can wave Specman objects in IES-XL *and* also save the wave setup for automatically restarting the simulation? If not, this tech tip is for you! Here is the process: Step 0 – Once you are happy with your waveform setup, don’t forget the basic step of saving your mix...

Posted to Functional Verification (Weblog) by teamspecman on Fri, Jan 22 2010
Formalizing Multilanguage Mixology For e Users

Historically it’s been very common for e users to have to mix other programming languages with their e verification environment. Some examples include adding C or C++ reference models, contributing e Universal Verification Components (UVCs) to non- e testbenches, or even interfacing to Matlab models...

Posted to Functional Verification (Weblog) by teamspecman on Thu, Dec 24 2009

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IES-XL,Specman

Inside Cadence: Training for EDA360

Informative Tweets on WHEN Inheritance

When Less Is More, Part 3: Is e code really “infinitely” more compact than SystemVerilog?

Built-in Message Logging – Part 1 of 2

Cadence Exec: Why Cadence is Comitted to e/Specman

DVCon 2010 For The Specmaniac

Beyond Coverage: Adding Arbitrary Metrics To Your Metric-Driven flow

Tech Tip: Easy Way To Re-Run Using The Same Seed

Tech Tip: Waving Specman Objects in SimVision

Formalizing Multilanguage Mixology For e Users