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IES-XL,OVM,SystemVerilog

IBM and Cadence Collaboration Improves Verification Productivity

Technology leaders like IBM continuously seek opportunities to improve productivity because they recognize that verification is a significant part of the overall SoC development cycle. Through collaboration, IBM and Cadence identify, refine, and deploy verification technologies and methodologies to improve...

Posted to Functional Verification (Weblog) by Adam Sherilog on Wed, Feb 13 2013
UVM SystemVerilog in a Multi-Language SoC World: UVM-ML Webinar

Every SoC project uses multiple languages. Even if the design itself is purely Verilog RTL, it's likely that you have some PLI-based stimulus. In many cases there are multiple languages in use due to multiple suppliers, globalized teams, multiple abstractions, and more. Integrating e , SystemVerilog...

Posted to Functional Verification (Weblog) by Adam Sherilog on Thu, Oct 11 2012
"We Want UVM 1.0! When Do We Want it? Now!"

Short of holding signs and yelling slogans, the 12 customers I visited in the past week all declared this mantra. All are planning to move to UVM 1.0 with all of them requiring the phasing and register package capabilities, but only one also requiring TLM2 support, primarily for accessing SystemC models...

Posted to Functional Verification (Weblog) by Adam Sherilog on Thu, Oct 7 2010
New UVM Book Is For You And U But Not Ewe

A Practical Guide to Adopting the Universal Verification Methodology (UVM) is the first book published on the emerging Accellera UVM . Written by the main authors of the user guide in the UVM release, this book provides more details and extends the methodology to address system level challenges. Unlike...

Posted to Functional Verification (Weblog) by Adam Sherilog on Wed, Jul 21 2010
Informative Tweets on WHEN Inheritance

Earlier today a lively and very instructive thread on the relative virtues of WHEN Inheritance developed on Twitter between @pmarriott (a D&V consultant in Montreal, Canada) , @yaron_think_ver (a verification consultant based in Israel) , and @teamspecman. Because this exchange was very technical...

Posted to Functional Verification (Weblog) by teamspecman on Tue, May 4 2010
When Less Is More, Part 2: Is e Code Really Up to 3x More Compact Than SystemVerilog?

In my last post I wrote some packet generation code to validate the claim that e code can be up to 3 times more compact vs. the equivalent functionality in SystemVerilog. The result was actually an e description that was more than 3x less than the SystemVerilog equivalent. In this post, let’s see...

Posted to Functional Verification (Weblog) by teamspecman on Tue, Apr 6 2010
When Less Is More, Part 1: Is e Really Up to 3x More Compact Than SystemVerilog?

A famous expression in the software world is that “you can only expect 10 good lines of production code per day”. Web search for this phrase and you will see there is ongoing debate whether this figure is still only 10 lines, or it’s improved to 20, or 100, or more. One thing that’s...

Posted to Functional Verification (Weblog) by teamspecman on Tue, Mar 30 2010
Cadence Exec: Why Cadence is Comitted to e/Specman

In case you or your management are wondering about Cadence's commitment to supporting the e language and/or Specman technology, allow us to direct your attention to this interview of Cadence Verification VP Mitch Weaver (who never worked for Verisity, BTW) by industry analyst Richard Goering. As...

Posted to Functional Verification (Weblog) by teamspecman on Tue, Feb 16 2010
DVCon 2010 For The Specmaniac

At next week's DVCon in San Jose, CA, Cadence will cover all aspects of our verification technologies and methodologies ( full list of Cadence-sponsored activities is posted here ). Of course, Team Specman is here help Specmaniacs discover the many activities that will feature Specman and e language...

Posted to Functional Verification (Weblog) by teamspecman on Mon, Feb 15 2010
AMIQ DVT Maximizes OVM Reuse Via Methodology Compliance

The Open Verification Component (OVC) defined by the official OVM User Guide in the OVM downloads enables the highest levels of reuse. While the OVM class libraries have the supporting classes for the OVC built-in, writing OVCs properly sits on the shoulders of the verification engineer. With Amiq's...

Posted to Functional Verification (Weblog) by Team genIES on Fri, Jan 8 2010

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IES-XL,OVM,SystemVerilog

IBM and Cadence Collaboration Improves Verification Productivity

UVM SystemVerilog in a Multi-Language SoC World: UVM-ML Webinar

"We Want UVM 1.0! When Do We Want it? Now!"

New UVM Book Is For You And U But Not Ewe

Informative Tweets on WHEN Inheritance

When Less Is More, Part 2: Is e Code Really Up to 3x More Compact Than SystemVerilog?

When Less Is More, Part 1: Is e Really Up to 3x More Compact Than SystemVerilog?

Cadence Exec: Why Cadence is Comitted to e/Specman

DVCon 2010 For The Specmaniac

AMIQ DVT Maximizes OVM Reuse Via Methodology Compliance