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IES-XL,OVM SV,OVM e

"We Want UVM 1.0! When Do We Want it? Now!"

Short of holding signs and yelling slogans, the 12 customers I visited in the past week all declared this mantra. All are planning to move to UVM 1.0 with all of them requiring the phasing and register package capabilities, but only one also requiring TLM2 support, primarily for accessing SystemC models...

Posted to Functional Verification (Weblog) by Adam Sherilog on Thu, Oct 7 2010
Inside Cadence: Training for EDA360

Over the past few weeks all of Cadence's Verification and Systems Solutions Applications Engineers (AEs), Services Engineers, and many Customer Support staff, have been brought together for detailed methodology and product training. The objectives of this ambitious undertaking are to bring their...

Posted to Functional Verification (Weblog) by jvh3 on Thu, May 6 2010
Informative Tweets on WHEN Inheritance

Earlier today a lively and very instructive thread on the relative virtues of WHEN Inheritance developed on Twitter between @pmarriott (a D&V consultant in Montreal, Canada) , @yaron_think_ver (a verification consultant based in Israel) , and @teamspecman. Because this exchange was very technical...

Posted to Functional Verification (Weblog) by teamspecman on Tue, May 4 2010
When Less Is More, Part 2: Is e Code Really Up to 3x More Compact Than SystemVerilog?

In my last post I wrote some packet generation code to validate the claim that e code can be up to 3 times more compact vs. the equivalent functionality in SystemVerilog. The result was actually an e description that was more than 3x less than the SystemVerilog equivalent. In this post, let’s see...

Posted to Functional Verification (Weblog) by teamspecman on Tue, Apr 6 2010
When Less Is More, Part 1: Is e Really Up to 3x More Compact Than SystemVerilog?

A famous expression in the software world is that “you can only expect 10 good lines of production code per day”. Web search for this phrase and you will see there is ongoing debate whether this figure is still only 10 lines, or it’s improved to 20, or 100, or more. One thing that’s...

Posted to Functional Verification (Weblog) by teamspecman on Tue, Mar 30 2010
Where’s The “You” In The OVM?

Cadence and Mentor have dedicated teams to the development and support of the OVM and you, our user community, have literally tens of thousands of developers dedicated to developing reusable VIP with it. But where do “you” and the OVM meet? Sometimes the “you” is obvious –...

Posted to Functional Verification (Weblog) by Adam Sherilog on Tue, Oct 27 2009
Why OVM? John Aynsley of Doulos Has 10 Reasons

Believe it or not, sometimes a marketing guy just needs to say less. It's true. It does happen. Sometimes we do just get right to the point. Yeah, we do blather on sometimes but ... oops, there I go again. Just listen to John. He has 10 great reasons to adopt the OVM. If video fails to play please...

Posted to Functional Verification (Weblog) by Adam Sherilog on Thu, Oct 22 2009

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IES-XL,OVM SV,OVM e

"We Want UVM 1.0! When Do We Want it? Now!"

Inside Cadence: Training for EDA360

Informative Tweets on WHEN Inheritance

When Less Is More, Part 2: Is e Code Really Up to 3x More Compact Than SystemVerilog?

When Less Is More, Part 1: Is e Really Up to 3x More Compact Than SystemVerilog?

Where’s The “You” In The OVM?

Why OVM? John Aynsley of Doulos Has 10 Reasons