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IES-XL,IES,OVM

IBM and Cadence Collaboration Improves Verification Productivity

Technology leaders like IBM continuously seek opportunities to improve productivity because they recognize that verification is a significant part of the overall SoC development cycle. Through collaboration, IBM and Cadence identify, refine, and deploy verification technologies and methodologies to improve...

Posted to Functional Verification (Weblog) by Adam Sherilog on Wed, Feb 13 2013
UVM SystemVerilog in a Multi-Language SoC World: UVM-ML Webinar

Every SoC project uses multiple languages. Even if the design itself is purely Verilog RTL, it's likely that you have some PLI-based stimulus. In many cases there are multiple languages in use due to multiple suppliers, globalized teams, multiple abstractions, and more. Integrating e , SystemVerilog...

Posted to Functional Verification (Weblog) by Adam Sherilog on Thu, Oct 11 2012
Holiday Idea #1: Give the Gift of UVM Knowledge

Your favorite verification engineer has been good all year. Thousands of tests run. Nights and weekends of debug. So how do reward her? Why, with UVM Training , of course! Cadence experts have trained hundreds of engineers on OVM and UVM. These trainers have deep knowledge in both the methodology and...

Posted to Functional Verification (Weblog) by Adam Sherilog on Tue, Dec 6 2011
"We Want UVM 1.0! When Do We Want it? Now!"

Short of holding signs and yelling slogans, the 12 customers I visited in the past week all declared this mantra. All are planning to move to UVM 1.0 with all of them requiring the phasing and register package capabilities, but only one also requiring TLM2 support, primarily for accessing SystemC models...

Posted to Functional Verification (Weblog) by Adam Sherilog on Thu, Oct 7 2010
AMIQ DVT Maximizes OVM Reuse Via Methodology Compliance

The Open Verification Component (OVC) defined by the official OVM User Guide in the OVM downloads enables the highest levels of reuse. While the OVM class libraries have the supporting classes for the OVC built-in, writing OVCs properly sits on the shoulders of the verification engineer. With Amiq's...

Posted to Functional Verification (Weblog) by Team genIES on Fri, Jan 8 2010
Why Verification Engineers Are Like Football Players

Is it their raw power? Is it the cheerleaders? Why are verification engineers like football players? It's because they know how to squeeze the maximum performance out of their resources to win the verification game. Charlie Dawson, Senior Engineering Manager at Cadence, has been leading teams that...

Posted to Functional Verification (Weblog) by Adam Sherilog on Fri, Oct 30 2009
Performance-Aware e Coding Guidelines – Part 5

In this last segment of the series on performance-aware coding, allow me to share with you two tips on improving the performance of Temporals. Temporals Performance Tip 1: Setup a "Synch Unit" If you don't already use a synch unit - I recommend you setup one up now. Here's why: the...

Posted to Functional Verification (Weblog) by teamspecman on Tue, Apr 28 2009
Performance-Aware e Coding Guidelines – Part 4

Specman 8.2s3 contains a new API to the sequence driver that enables users to improve the performance of stimulus creation. With this API you can create stimulus items in an efficient manner, and reduce the number of context switches between the sequence and its driver. For example, instead of many generation...

Posted to Functional Verification (Weblog) by teamspecman on Thu, Apr 16 2009
DVCon 2009 - Day 1

As promised, here is my photo blog of Day 1 of DVCon, focused on the OVM Multi-Language tutorial and the show floor . While I've added descriptive captions to the photos, here are some quick takes: * Adam, Brett, and the others at the OVM Multi-Language tutorial reported that the session was very...

Posted to Functional Verification (Weblog) by jvh3 on Wed, Feb 25 2009

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IES-XL,IES,OVM

IBM and Cadence Collaboration Improves Verification Productivity

UVM SystemVerilog in a Multi-Language SoC World: UVM-ML Webinar

Holiday Idea #1: Give the Gift of UVM Knowledge

"We Want UVM 1.0! When Do We Want it? Now!"

AMIQ DVT Maximizes OVM Reuse Via Methodology Compliance

Why Verification Engineers Are Like Football Players

Performance-Aware e Coding Guidelines – Part 5

Performance-Aware e Coding Guidelines – Part 4

DVCon 2009 - Day 1