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IES-XL,Functional Verification,methodology

UVM Testflow Phase Debugging- Identifying Blocking Activities

UVM Testflow debugging capabilities have been recently enhanced through the addition of more information to the output of the show domain command. In this post, we demonstrate how this information can be used to answer such questions as 1. What domains are in the environment? What units do they contain...

Posted to Functional Verification (Weblog) by teamspecman on Mon, Jul 16 2012
Video: Update on AMIQ’s DVT IDE and UVM 1.0 at DVCon 2011

The UVM 1.0 release was the big story of DVCon 2011, as it's the first verification methodology officially supported by all three of the "Big 3" simulation vendors. However, the very nature of the standard -- an open source library governed by a community similar in character to Linux itself...

Posted to Functional Verification (Weblog) by jvh3 on Wed, Apr 6 2011
e Verification Job Postings We’ve Seen

Specmaniacs between jobs: over the last few weeks we’ve seen job postings for verification engineering in general, and e/Specman expertise in specific, in the LinkedIn groups: “Experts in SystemVerilog/Specman/VERA/System C” “Think Verification” “HVL (SystemC/C++/Verilog...

Posted to Functional Verification (Weblog) by teamspecman on Fri, Aug 6 2010
Specman, e, and EDA360

The EDA industry is all abuzz over the new vision paper "EDA360 - The Way Forward for Electronic Design" ; and for good reason - in 2010 the electronics world is finally starting to transform in ways that have been long anticipated by Specmaniacs and our "Trailblazer" program partners...

Posted to Functional Verification (Weblog) by teamspecman on Tue, Jun 8 2010
Formalizing Multilanguage Mixology For e Users

Historically it’s been very common for e users to have to mix other programming languages with their e verification environment. Some examples include adding C or C++ reference models, contributing e Universal Verification Components (UVCs) to non- e testbenches, or even interfacing to Matlab models...

Posted to Functional Verification (Weblog) by teamspecman on Thu, Dec 24 2009

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IES-XL,Functional Verification,methodology

UVM Testflow Phase Debugging- Identifying Blocking Activities

Video: Update on AMIQ’s DVT IDE and UVM 1.0 at DVCon 2011

e Verification Job Postings We’ve Seen

Specman, e, and EDA360

Formalizing Multilanguage Mixology For e Users