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IES-XL,Accellera VIP TSC

  • Holiday Idea #1: Give the Gift of UVM Knowledge

    Your favorite verification engineer has been good all year. Thousands of tests run. Nights and weekends of debug. So how do reward her? Why, with UVM Training , of course! Cadence experts have trained hundreds of engineers on OVM and UVM. These trainers have deep knowledge in both the methodology and...
    Posted to Functional Verification (Weblog) by Adam Sherilog on Tue, Dec 6 2011
  • "We Want UVM 1.0! When Do We Want it? Now!"

    Short of holding signs and yelling slogans, the 12 customers I visited in the past week all declared this mantra. All are planning to move to UVM 1.0 with all of them requiring the phasing and register package capabilities, but only one also requiring TLM2 support, primarily for accessing SystemC models...
    Posted to Functional Verification (Weblog) by Adam Sherilog on Thu, Oct 7 2010
  • New UVM Book Is For You And U But Not Ewe

    A Practical Guide to Adopting the Universal Verification Methodology (UVM) is the first book published on the emerging Accellera UVM . Written by the main authors of the user guide in the UVM release, this book provides more details and extends the methodology to address system level challenges. Unlike...
    Posted to Functional Verification (Weblog) by Adam Sherilog on Wed, Jul 21 2010
  • DAC360: Photo blog of DAC 2010 in Anaheim, CA

    Click here or on the image below to go to the annotated photo blog of DAC 2010. Images and notes include highlights from: * The Cadence and OVM/UVM booths * Sites around the show floor * Things outside of the expo, including panels, papers, and presentations (Yes, there is more to DAC than booths!) Enjoy...
    Posted to Functional Verification (Weblog) by jvh3 on Tue, Jun 22 2010
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