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Launch Time – Udacity CS348 Functional Hardware Verification Hits the Web Today, March 12, 2013
Coinciding with the first day of CDNLive! Silicon Valley, our Udacity MOOCs course on Functional Hardware Verification will go live today! Developing this course has been a very rewarding experience and we are happy this day has finally come. Last week we gave you a sneak preview of the interactivity...
Posted to
Functional Verification
(Weblog)
by
Axel Scherer
on Tue, Mar 12 2013
JBYOB (Just Bring Your Own Browser): Interactive Labs on Udacity CS348 Functional Hardware Verification – No Installation Required
On February 19, we announced the launch date for our Udacity MOOCs course: CS348 Functional Hardware Verification , which will launch in exactly one week from now on March 12, 2013. When we communicated the launch date, we also released the first clip of the first unit. Now we want to give you a glimpse...
Posted to
Functional Verification
(Weblog)
by
Axel Scherer
on Tue, Mar 5 2013
It’s Coming: Udacity CS348 Functional Hardware Verification Course Launches on March 12, 2013
On October 18, 2012 Google, NVIDIA, Microsoft, Autodesk, Cadence and Wolfram announced their collaboration with Udacity . Working with Udacity, each of the companies listed above is developing new massive open online courses ( MOOCs ). The Cadence contribution is CS348 Functional Hardware Verification...
Posted to
Functional Verification
(Weblog)
by
Axel Scherer
on Tue, Feb 19 2013
Need e/Specman Expertise ASAP? Free Training and Verification Alliance Partners Are Available Now
Recently an EDA industry observer relayed some Specmaniacs' concerns about satisfying the increasing demand for e/Specman trained verification engineers in Europe and other geographies. Team Specman is seeing this growth too, and here is what we [Cadence] are doing to help: * First, we have a network...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Fri, Nov 16 2012
Do you MOOC? Expanding Access to e (IEEE 1647) Verification Training Globally
Two of the key factors for successful and productive simulation-based hardware verification are an efficient verification language and an associated methodology. As the global design and verification eco system is scattered and evolving rapidly, it is hard to keep all engineers trained. We are looking...
Posted to
Functional Verification
(Weblog)
by
Axel Scherer
on Thu, Oct 18 2012
UVM SystemVerilog in a Multi-Language SoC World: UVM-ML Webinar
Every SoC project uses multiple languages. Even if the design itself is purely Verilog RTL, it's likely that you have some PLI-based stimulus. In many cases there are multiple languages in use due to multiple suppliers, globalized teams, multiple abstractions, and more. Integrating e , SystemVerilog...
Posted to
Functional Verification
(Weblog)
by
Adam Sherilog
on Thu, Oct 11 2012
What Does it Take to Migrate from e to UVMe?
So you are developing your verification environment in e , and like everyone else, you've been hearing a lot of buzz surrounding UVM (Universal Verification Methodology). Maybe you would also like to give it a try. The first question that pops in your mind is, "What would it take to migrate...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Wed, Sep 5 2012
Constrained Random Test Generation In e [IEEE 1647], Ernie * Duracell ≈ Infinity Minus
Ernie & Duracell "I feel great" - long pause - "I feel great, I feel great". 6 weeks later: "I feel great, I feel great, I feel great" - pause - "I feel great". I hear this sound coming out of my son's room. What is going on in my house? Is there such a...
Posted to
Functional Verification
(Weblog)
by
Axel Scherer
on Wed, Aug 1 2012
Global Cowbell Fever Spreads – We Are Launching 12 “UVM SystemVerilog Basics” Videos in Chinese
A little over two and a half months ago we started sounding the "cowbell" with the release of the UVM SystemVerilog Basics videos . The resonance has been strong. As there can (almost) never be too much of a good thing, we are expanding this series by re-releasing the videos audio dubbed into...
Posted to
Functional Verification
(Weblog)
by
Axel Scherer
on Mon, Jul 23 2012
My Clark Kent Moment – How I Discovered Aspect Oriented Programming in e (IEEE 1647)
Growing up on VHDL, moving on to Verilog and then to SystemVerilog, I eventually discovered e (IEEE 1647) Initially I thought: "What is the fuss all about?" While exploring the language during the development of the cowbell videos , it hit me -- I started to recognize the power of Aspect Oriented...
Posted to
Functional Verification
(Weblog)
by
Axel Scherer
on Tue, Jul 10 2012
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