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IEEE 1647

UVM e (IEEE 1647) Video Series Features the Return of the Cowbell!

A significant number of readers of my previous post on this topic were not aware of the Saturday Night Live cowbell skit. This took me quite by surprise! The only prescription for this problem is that I pledge to continue to play the cultural ambassador and will introduce more vital trivia! However,...

Posted to Functional Verification (Weblog) by Axel Scherer on Mon, May 21 2012
Q&A: 7 Years After Verisity – How Specman and e Language Changed IC Verification

Seven years ago this month (April 2005) Cadence acquired Verisity, the pioneering verification company that developed the e language and the Specman environment. The acquisition resulted in a paradigm shift in IC verification, setting the stage for reusable verification methodologies, constrained-random...

Posted to Industry Insights (Weblog) by rgoering on Tue, Apr 24 2012
2011 EDA Standards Update and 2012 Forecast

As system complexity grows and semiconductor process nodes shrink, EDA industry standards are more important than ever. With today's time-to-market pressures, the last thing you'd want to do is waste time due to incompatible formats, tools or methodologies. Fortunately, 2011 was a productive...

Posted to Industry Insights (Weblog) by rgoering on Wed, Dec 21 2011
Is e Old? Yes. Is it Outdated? Definitely Not!

I was at the Design Automation Conference (DAC) last week showcasing our latest, greatest Incisive Enterprise Simulator (IES) performance features in the demo suites. In my "off" time, I was in our DAC booth meeting customers and discussing our advanced verification solutions. I ran into a...

Posted to Functional Verification (Weblog) by teamspecman on Thu, Jun 16 2011
e Templates: A Nifty Way To Create Reusable Code

Hi All, An e template (known as a parameterized type in other programming languages) is a feature that has been around for several releases and can be a great way of creating re-usable code. Templates can be used anywhere a user would like to create a single re-useable object that might operate on different...

Posted to Functional Verification (Weblog) by teamspecman on Tue, Aug 10 2010
e Verification Job Postings We’ve Seen

Specmaniacs between jobs: over the last few weeks we’ve seen job postings for verification engineering in general, and e/Specman expertise in specific, in the LinkedIn groups: “Experts in SystemVerilog/Specman/VERA/System C” “Think Verification” “HVL (SystemC/C++/Verilog...

Posted to Functional Verification (Weblog) by teamspecman on Fri, Aug 6 2010
When Less Is More, Part 3: Is e code really “infinitely” more compact than SystemVerilog?

Building on the packet generation example of part 1 , and the coverage examples of part 2 that compare the ratio of lines e code to lines of SystemVerilog for a given task, in this post I’m going to show you how to “divide by 0” and leverage e capabilities that simply don’t exist in SystemVerilog, technically...

Posted to Functional Verification (Weblog) by teamspecman on Wed, Apr 21 2010
Specman-SimVision webinar on April 22 (next week!)

We interrupt Corey's excellent "When Less Is More" series to announce a Specman-SimVision webinar next week, April 22 at 10:00AM Pacific time. In short, if you’ve been using Specview with Specman/ e and would like to learn all the key advantages of using the SimVision debug tool,...

Posted to Functional Verification (Weblog) by teamspecman on Tue, Apr 13 2010
When Less Is More, Part 2: Is e Code Really Up to 3x More Compact Than SystemVerilog?

In my last post I wrote some packet generation code to validate the claim that e code can be up to 3 times more compact vs. the equivalent functionality in SystemVerilog. The result was actually an e description that was more than 3x less than the SystemVerilog equivalent. In this post, let’s see...

Posted to Functional Verification (Weblog) by teamspecman on Tue, Apr 6 2010
When Less Is More, Part 1: Is e Really Up to 3x More Compact Than SystemVerilog?

A famous expression in the software world is that “you can only expect 10 good lines of production code per day”. Web search for this phrase and you will see there is ongoing debate whether this figure is still only 10 lines, or it’s improved to 20, or 100, or more. One thing that’s...

Posted to Functional Verification (Weblog) by teamspecman on Tue, Mar 30 2010

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IEEE 1647

UVM e (IEEE 1647) Video Series Features the Return of the Cowbell!

Q&A: 7 Years After Verisity – How Specman and e Language Changed IC Verification

2011 EDA Standards Update and 2012 Forecast

Is e Old? Yes. Is it Outdated? Definitely Not!

e Templates: A Nifty Way To Create Reusable Code

e Verification Job Postings We’ve Seen

When Less Is More, Part 3: Is e code really “infinitely” more compact than SystemVerilog?

Specman-SimVision webinar on April 22 (next week!)

When Less Is More, Part 2: Is e Code Really Up to 3x More Compact Than SystemVerilog?

When Less Is More, Part 1: Is e Really Up to 3x More Compact Than SystemVerilog?