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  • CDR for USB 3.0 PHY

    Sir, I am modeling a Dual loop CDR for USB 3.0 PHY. As per jitter budgeting of USB 3.0, it specifies a deterministic jitter of 143pSec and random jitter of 4.03pSec. As I was trying to model random jitter using Verilog A function $dist_normal (seed, mean, sd) with mean=0 and sd=4.03p and similarly deterministic...
    Posted to Custom IC Design (Forum) by Jithin on Tue, May 20 2014
  • IC610 on SLES11

    Hi, I am trying to use IC610 on SLES11 as SLES10 is totally discontinued! Are there any know issues I should be worried about? The OS support matrix says SLES11 does not support IC610. I tired to invoke virtuoso with IC610 on SLES11 its working fine so far. Thank You
    Posted to Custom IC Design (Forum) by msvlsi on Mon, Oct 22 2012
  • DIVA LVS Error

    Forum users, I've created a schematic and layout of a simple cell using IC6.1.0 and trying to perform DIVA LVS by invoking it from the Virtuoso Layout L window by selecting Verify->LVS... I am getting an error that I think signifies that the layout is failing to netlist. Please see attached figure...
    Posted to Custom IC Design (Forum) by saullacour on Mon, Apr 23 2012
  • Aging simulation with RelXpert and Eldo

    Hello everyone I would like to simulate the aging behavior on circuit-level of the circuits built by bulk-Si CMOS technology. I know that there is a tool named “RelXpert” (combined with UltraSim) in Analog Design Environment (ADE) of Cadence Virtuoso can be used for aging (NBTI and HCI) simulation...
    Posted to Custom IC Design (Forum) by SilentHunter on Sun, May 15 2011
  • error when launching cadence IC610

    Hi everyone, I just installed IC610 on our Linux machine (radhat enterprise5, 64bit) . We have a IC5141 on it already by the way. I got error when I tried to run the IC610. I put "virtuoso" and error information comes: /cadence/IC610/tools/dfII/32bit/virtuoso: symbol lookup error: /cadence...
    Posted to Custom IC Design (Forum) by Sindy on Sat, Apr 9 2011
  • ADE hangs up when java is running

    Dear Cadence-Experts, I have a problem with the ADE (Analog Design Environment) running within a newly installed Cadence software (IC 6.1.3, MMSIM 7.01, IUS 8.10 under RedHat 4 on Intel Core i7 CPU 950). Problem scenario 1: * A quick way to trigger the problem is to try to change the "Project Directory"...
    Posted to Custom IC Design (Forum) by Michael2010 on Thu, Nov 25 2010
  • ADE L 6.1.4 Parametric/MonteCarlo Sweep

    I will soon help with evaluation of the 6.1 version of cadence. To maximize the time I have for evaluation, I have some general questions. In the new version, the model sections can be set with a design variable using VAR. From reading the manuals, a few of things are not clear to me: 1) Can this design...
    Posted to Custom IC Design (Forum) by MarkSummers on Sun, Jun 27 2010
  • How to identify version of simulator?

    Guys, In IC ver 610 , how to identify the version of simulator installed? and also list of simulators available? Please propose some easy way since I'm beginner in this software. Thank you very much. regards, M.Kumar
    Posted to Custom IC Design (Forum) by KumarMK on Wed, Feb 10 2010
  • Problem with Simulating Design using Spectre

    I have created a schematic using Virtuoso 6. When I open the ADE, it says "(deLicense-7) Could not get a license for ADE L. Would you like to try to get a higher-tiered license to run this product?" When I click on Yes, it starts the ADE, but when I set up the analysis and click on "Netlist...
    Posted to Custom IC Design (Forum) by govilv on Thu, Jun 4 2009
  • VerilogA Problem in MMSIM-7.1

    Hi, I am having a problem to simulate my verilogA files under MMSIM 7.1. They work fine under MMSIM-6.0. In spectreout, I get: ERROR (VACOMP-1008): Cannot compile ahdlcmi module library. Check the log file input.ahdlSimDB/3821_soi12so_Test_Tapeout_Sept09_BinarySearch_veriloga_veriloga.va.BinSearch.ahdlcmi...
    Posted to Custom IC Design (Forum) by gokce on Wed, Jun 3 2009
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