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IC610,Analysis

  • CDR for USB 3.0 PHY

    Sir, I am modeling a Dual loop CDR for USB 3.0 PHY. As per jitter budgeting of USB 3.0, it specifies a deterministic jitter of 143pSec and random jitter of 4.03pSec. As I was trying to model random jitter using Verilog A function $dist_normal (seed, mean, sd) with mean=0 and sd=4.03p and similarly deterministic...
    Posted to Custom IC Design (Forum) by Jithin on Tue, May 20 2014
  • How to identify version of simulator?

    Guys, In IC ver 610 , how to identify the version of simulator installed? and also list of simulators available? Please propose some easy way since I'm beginner in this software. Thank you very much. regards, M.Kumar
    Posted to Custom IC Design (Forum) by KumarMK on Wed, Feb 10 2010
  • Error in Virtuoso..

    Hi all.. I got this error while designing, I have never encountered it before. Can anyone help me ? Loading /opt/cadence/IC5141/tools.lnx86/cmi/lib/4.0/libinfineon_sh.so ... Loading /opt/cadence/IC5141/tools.lnx86/cmi/lib/4.0/libnortel_sh.so ... Loading /opt/cadence/IC5141/tools.lnx86/cmi/lib/4.0/libphilips_sh...
    Posted to Custom IC Design (Forum) by kgulur on Sat, Sep 27 2008
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