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  • High capacity IR analysis problems

    Hi, I'm using IC6.15-64b.500.6 on openSUSE 11.4. I'm trying to carry out a high capacity analogue IR drop analysis but am running into problems. I've successfully done "regular" IR drop analyses in the past using an extracted view and a post layout simulation but haven't used...
    Posted to Custom IC Design (Forum) by oojah on Fri, Oct 26 2012
  • How to streamout a gds and will have an output that is flattened

    Hi, I need a flattened GDS output from a stream out in IC6.1.5, the usual output of the File>Export>Stream is a GDS file with Hierarchical information. Can anyone tell me how to have an output gds file which is in a flattened state?. Thanks...
    Posted to Custom IC Design (Forum) by jorenrefuerzo on Thu, Oct 11 2012
  • How to simulate the Noise figure in Pnoise from 1 stage to another?

    Hi there, I want to simulate the Noise figure for such a setup that first a band pass filter, then sample and hold, and then follower by amplifier, and ADC and so on. Can i get the noise figure from source to each stage with Pnoise? I understand that if the output is specified with voltage of two node...
    Posted to Custom IC Design (Forum) by zcam on Fri, Sep 28 2012
  • Cellviews missing cdb2oa

    Hello, I convert a design from IC5.1 to IC6.1.5 and I see that three OA cells have no views in the library manager. I try to translate this cells again with different parameters, but they are still empty (each cell has two views in CDB: 'abstract' ans 'layout'). The log file says that...
    Posted to Custom IC Design (Forum) by benben6688 on Wed, Sep 12 2012
  • cdb2oa warnings

    Hello, I want to convert a design from IC5.1 to IC6.1.5.72 with cdb2oa, and I encounter this warnings: Warning (Technology Conversion) : rtuosoIccInfo : Layer AP has preferred routing direction 'horizontal'. Cannot set to 'orthogonal'. Warning (Technology Conversion) : rtuosoIccInfo ...
    Posted to Custom IC Design (Forum) by benben6688 on Tue, Sep 11 2012
  • Re: RE: RE: Transient simulation taking too much memory

    Hi vshssvs7, Please note that Cadence AEs respond to questions on this forum often "off hours" and/or in addition to their "regular duties". If this is a critical issue and you need immediate attention, please talk to your University staff and see how to file a Service Request at...
    Posted to Custom IC Design (Forum) by Tawna on Mon, Jun 4 2012
  • cdb2oa (PcellEvalFail)

    Hi Masters, I'm facing issue when dealing with cdb2oa. I can't retain my cdf callback after converting my layout from cdb to oa database;resulted PcellEvailFail message show up... Below is one of the ERROR message. ERROR (CDBOA-603): Cellview <path>/<name> contains <object type>...
    Posted to Custom IC Design (Forum) by Peter123 on Tue, May 22 2012
  • APS, Multi-threading, High-Performance Simulation...

    Andrew, I am a bit confused with all of the high performance simulation options in ADE-XL/GXL. I am using IC with MMSIM 10.11.200 On ADE I have: 1. "Options->Job Setup->Max Jobs" 2. "Options->Run Options-> Run In" 3. "High-Performance Simulation->Mode...
    Posted to Custom IC Design (Forum) by aditeman on Mon, May 14 2012
  • High frequency quadrature VCO design with good phase noise

    Hello everyone I am a newbie engineer starting my career in RF IC design and working on designing a high frequency VCO (38 GHz) with good phase noise characteristics. I am using Cadence IC6.1.5-64b.500 version and spectre simulator for the schemtic design and simulations. I have to do everything from...
    Posted to Custom IC Design (Forum) by rohan kr on Thu, Mar 29 2012
  • Strange behavior of constraint manager for instance bus

    Hi I am trying to create constraints on a top level cell which contains some instance buses in it. for nets in the top level and for nets in subcell which are not bused instances, the selection works fine and I am able to create constraints correctly. However if I go down an instance bus and select a...
    Posted to Custom IC Design (Forum) by Rushang on Thu, Nov 10 2011
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