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IC6.1.5

  • OCEAN script generated for AMS + APS simulation

    Hi all, I was recently working on a mixed-singal simulation with AMS. To speed up the simulation, in ADE, I chose simulation performance mode as "APS", and manually chose 8 threads. In ADE, everything goes well, 8 cpu cores were brought up for the simulation, the simulation finished quite soon...
    Posted to Custom IC Design (Forum) by alleyor on Thu, Nov 14 2013
  • Is there a way in Verilog-A to know if transient noise analysis is run?

    Hi. I'm running IC6.1.5.500.12 with MMSIM 12.1.0.435.isr7. I know the 'if (analysis("tran"))' Verilog-A statement can be used to select code to run when transient analysis is run, but how do I tell in Verilog-A if transient noise analysis is run? Is there some other option for the...
    Posted to Custom IC Design (Forum) by SharksFan on Thu, Sep 19 2013
  • license virtuoso schematic editor XL

    Hello, I am working with Cadence 6.1.5 . We have the license for virtuoso schematic editor XL. When I create a schematic view cell or a verilogA view, I get this message " could not get license virtuoso schematic editor L" and no window is open nor a view is created. What I understood is that...
    Posted to Custom IC Design (Forum) by kjabeur on Tue, Jul 23 2013
  • CDB to OA Conversion: Layout Issue

    Hi, Cadence version: IC6.1.5 Lately, we have been converting our design database from IC5 to IC6, using cdb2oa script, that was shipped along with IC6. We managed to convert the database without any error. The schematic in OA matched perfectly to its CDB counterpart, but not for the layouts. Most of...
    Posted to Custom IC Design (Forum) by sebastion on Tue, Apr 30 2013
  • Problem in Cadence Virtuoso AC analysis

    Hi all, I am facing an often discussed problem while simulating a differential pair in cadence virtuoso. Though I have biased the transistors through DC (though they are in subthreshold mode), yet when I try do do ac analysis (I follow all regular steps) I get a zero magnitude at output. Ths schematic...
    Posted to Custom IC Design (Forum) by OneNewBoy on Thu, Mar 21 2013
  • How to change wire's collor in Virtuso Schematic Editor

    Is it possible to change individual collor for wire in Virtuoso Schematic Editor (rev. 6.1.5)? I need several types of wires to visualize voltage and analog-digital domains. The same question about collor of shapes (e.g. lines in symbol) - is it possible to change their collors individually?
    Posted to Custom IC Design (Forum) by Runner on Sun, Mar 3 2013
  • Layout cell checked out warnings because of rulers.

    Few of the cells I opened in read mode and when drawn a ruler are thought to be checked out through design sync. But actually I did not make any changes to the layout cell. Even after I open up the cell and clear rulers(I made the ruler not selectable during the setup), it keeps me giving that warning...
    Posted to Custom IC Design (Forum) by fun4skilled on Wed, Feb 6 2013
  • Cell modified

    Few of the cells I opened in read mode and when drawn a ruler are thought to be checked out through design sync. But actually I did not make any changes to the layout cell. Even after I open up the cell and clear rulers, it keeps me giving that warning when ever I close the data or try to do a stream...
    Posted to Custom IC Design (Forum) by fun4skilled on Wed, Feb 6 2013
  • delay in simulation initialization in ADE-XL

    Hi Andrew, We have a small but aggravating issue in running simulations on ADE-XL with IC6.1.5/MMSIM 10.11 When we run a simulation by pressing the green "play" button in the old fashioned test editor (opened from ADE-XL), the simulation starts to run instantly, as expected. But when we run...
    Posted to Custom IC Design (Forum) by aditeman on Wed, Nov 28 2012
  • High capacity IR analysis problems

    Hi, I'm using IC6.15-64b.500.6 on openSUSE 11.4. I'm trying to carry out a high capacity analogue IR drop analysis but am running into problems. I've successfully done "regular" IR drop analyses in the past using an extracted view and a post layout simulation but haven't used...
    Posted to Custom IC Design (Forum) by oojah on Fri, Oct 26 2012
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