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IC6.1.5,NMOS

  • Problem in Cadence Virtuoso AC analysis

    Hi all, I am facing an often discussed problem while simulating a differential pair in cadence virtuoso. Though I have biased the transistors through DC (though they are in subthreshold mode), yet when I try do do ac analysis (I follow all regular steps) I get a zero magnitude at output. Ths schematic...
    Posted to Custom IC Design (Forum) by OneNewBoy on Thu, Mar 21 2013
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