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IC6.1.4,layout

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  • Layout of Triple Well NFET without Pcell

    Hello all, I was recently tasked with drawing Pcells of nfetxs layer by layer. I successfully completed a generic nfetx, but am having difficultly with the nfettwx. I have gotten the triple well (nfettwx) to pass DRC with no errors, however, when I run the LVS (Assura) errors pop up. They are: *ERROR...
    Posted to Custom IC Design (Forum) by bnugent on Thu, Jun 9 2011
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