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IC6.1.4

  • How to compile verilog file to valid IC6.x cellview from command prompt

    Hi, I need to compile verilog files to valid IC6.x cellviews from command prompt (batch file). In IC5.x I used command “ncvlog –use5x...” to compile existing verilog file to valid cellview In IC6.x with ncvlog 11.1 cellview still criated in format of IC5.x . It meens no netlist.oa and...
    Posted to Custom IC Design (Forum) by aleksand1975 on Wed, Aug 15 2012
  • Problems during ADE simulation

    Hello, i am tring to run a simple simulation about a inverter, following a guide books. i am using ic614 and mmsim61. After starting simulatio, error occured, and I get the following message: " *Error* Errors encountered during simulation.The simulator run log has not been generated. possible cause...
    Posted to Custom IC Design (Forum) by erangle on Mon, May 28 2012
  • How to set the senstype during sens analysis in ADE L?

    hello,everybody: After I use the sensitivity analysis in ADE L, I print the sens result in the result box. Then, I found that the sensitivity result is given by S(F,P)=dF/dP rather than S(F,P)=P/F * dF/dP And, after I search it in many references, I find that the value of senstype would deside which...
    Posted to Custom IC Design (Forum) by amwygah on Tue, Oct 4 2011
  • Layout of Enclosed Gate Transistors (EGTs or ELTs)

    Hello, I'm designing an enclosed layout transistor but can not pass both DRC and LVS. I'm running IBM's PDK cmrf7sf V1.8.0.6 ML, out of virtuoso rev 6.1.4, and my simulator is Assura. Does anyone have any experience in getting a ELT to pass DRC and LVS in this process? Any help would be greatly...
    Posted to Custom IC Design (Forum) by bnugent on Wed, Jun 15 2011
  • Layout of Triple Well NFET without Pcell

    Hello all, I was recently tasked with drawing Pcells of nfetxs layer by layer. I successfully completed a generic nfetx, but am having difficultly with the nfettwx. I have gotten the triple well (nfettwx) to pass DRC with no errors, however, when I run the LVS (Assura) errors pop up. They are: *ERROR...
    Posted to Custom IC Design (Forum) by bnugent on Thu, Jun 9 2011
  • Fonts are not visiable in Virtuoso LSW & property editors

    Dear Experts, I'm facing the following problems with Virtuoso version# IC61.4.500.5: When invoking Virtuoso the following error window appears: LE-107020 Not a layout window. Closing it and opening any layout, in LSW and in property editors fonts appears as empty rectangles. It looks like that the...
    Posted to Custom IC Design (Forum) by AnnaS on Thu, May 26 2011
  • Aging simulation with RelXpert and Eldo

    Hello everyone I would like to simulate the aging behavior on circuit-level of the circuits built by bulk-Si CMOS technology. I know that there is a tool named “RelXpert” (combined with UltraSim) in Analog Design Environment (ADE) of Cadence Virtuoso can be used for aging (NBTI and HCI) simulation...
    Posted to Custom IC Design (Forum) by SilentHunter on Sun, May 15 2011
  • IC6.1.4 cds_thru netlist problem

    I have a schematic in IC6.1.4 that uses two cds_thru instances. These two instances connect a single node to two output pins. When I neltist the schematic using CDL Out, the one cds_thru is replaced by a short circuit, and the other by a 100m resistor. Although this is not consistent, my design wiil...
    Posted to Custom IC Design (Forum) by TjaartOpperman on Fri, Feb 25 2011
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