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IC6.1.4,assura LVS

  • Layout of Enclosed Gate Transistors (EGTs or ELTs)

    Hello, I'm designing an enclosed layout transistor but can not pass both DRC and LVS. I'm running IBM's PDK cmrf7sf V1.8.0.6 ML, out of virtuoso rev 6.1.4, and my simulator is Assura. Does anyone have any experience in getting a ELT to pass DRC and LVS in this process? Any help would be greatly...
    Posted to Custom IC Design (Forum) by bnugent on Wed, Jun 15 2011
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