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IC design,in-design signoff

  • Taming the Challenges of IC Design

    AUSTIN, Texas--You want the bad news first or the good news about IC design challenges? Let's start with the bad news: As IC design moves into 20nm and 16nm nodes, the challenges facing not only designers but EDA vendors are extraordinary if the industry is to maintain momentum and design productivity...
    Posted to The Fuller View (Weblog) by Brian Fuller on Wed, Jul 24 2013
  • Whitepaper: New Methodology Needed for 20nm Custom/Analog IC Design

    Before digital SoC designers take advantage of the power, performance and density advantages of 20nm, custom/analog designers must develop the standard cells and the analog/mixed-signal IP. Thus, no 20nm solution is complete without an integrated custom/analog capability. A newly published Cadence whitepaper...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Nov 13 2012
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