Home > Community > Tags > IC Design/signoff
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

IC Design,signoff

  • Tackling Complexity at the System-to-Silicon Verification Summit

    System-to-silicon verification is the biggest challenge our industry faces today. It's also the biggest opportunity for both design teams and EDA vendors. Consider the productivity and time-to-market improvements that we could yield in the coming years if everything goes according to plan. (In fact...
    Posted to The Fuller View (Weblog) by Brian Fuller on Tue, Sep 24 2013
  • Taming the Challenges of IC Design

    AUSTIN, Texas--You want the bad news first or the good news about IC design challenges? Let's start with the bad news: As IC design moves into 20nm and 16nm nodes, the challenges facing not only designers but EDA vendors are extraordinary if the industry is to maintain momentum and design productivity...
    Posted to The Fuller View (Weblog) by Brian Fuller on Wed, Jul 24 2013
Page 1 of 1 (2 items)