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IC 6.1
A/MS
ADE
ADE-GXL
ADE-XL
advanced node
AMS
AMS Designer
AMS Verification
AMS-Designer
analog
Analog Design Environment
analog behavioral models
analog behavoral
Analog Design Environment
analog on top
Analog simulation
analog/mixed-signal
APS
ARM
ARM Cortex M0
ARM-Cortex-M
Bleasdale
CAA
CDNLive SV 2012
CDNLive!
change
chip optimizer
Circuit Design
Cliosoft
CMP
Common Power Format
Connectivity-driven
Constraint-driven
corners
Corners analysis
Cortex-M
Cortex-M0
CPF
Cusstom IC Design
Custom IC Design
custom/analog
design implementation
DFM
DFY
drag and drop
ECO
ECOs
ECOs and PCells
EDI
EDIS
Encounter
Exceed on Demand
floorplanning
IC 6.1.4
IC 6.1.5
IC615
LDE
Litho
low power
mixed signal
mixed signal design
mixed-signal
oa
open access
OpenAccess
parasitic
Schematic-driven Layout
Search Assistant
signoff
simulation
SKILL
SKILL++
space based router
Spectre
STA
static timing analysis
Tech on Tour
thumbnails
timing model
TowerJazz
UVM
variability
Variability Aware Design
variation
verification
Verilog-AMS
Virtuoso
Virtuoso Advanced Node
Virtuoso Analog Design Environment
VIrtuoso drag and drop
Virtuoso environment
Virtuoso IC 6.1.3
Virtuoso IC6.1.5
Virtuoso Layout Suite GXL
Virtuoso Space-based Router
Virtuoso-AMS
Viva
ViVa-XL
VSR
worst case corners
Things You Didn't Know About Virtuoso: Managing Your Real Estate - Part 2
I keep my toothpaste in my bathroom. I keep the paprika in the kitchen. I keep the band-aids in the bathroom near the living room. Two points here. First, I keep the tools I need near the place where I do the activity for which I might need them. Second, I try to always keep things in the same place...
Posted to
Custom IC Design
(Weblog)
by
stacyw
on Tue, Jun 16 2009
Part 1 - Constraint-driven Physical Design Speeds Custom IC Design Convergence
In this introductory Part I of V of this blog I will discuss the advanced node design challenges impacting CIC design convergence and the solutions to achieve expedited physical implementation convergence. As designers move to 65nm technologies and below, the convergence of performance-driven design...
Posted to
Custom IC Design
(Weblog)
by
craigth
on Wed, Apr 15 2009
What’s all the Hoopla with PDKs?
At a purely technical level, Process Design Kits are fairly innocuous. They are used to enable custom IC design flows. A Process Design Kit (PDK) includes device models, schematic symbols, netlisting procedures and parameterizable cell layout generators. Physical verification rule decks and a parasitic...
Posted to
Custom IC Design
(Weblog)
by
Robin Sarma
on Tue, Mar 31 2009
Page 4 of 4 (33 items)
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