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IC packaging
"PCB design"
16.6
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Make Your IC Packaging Documentation Labels Smarter with 16.6 SiP and APD
Documentation is key when completing any IC package substrate design. Without it, any number of problems can arise - from incorrect bond mapping between die pads and bond fingers to die being stacked in the wrong order. Ensuring that your documentation text labels are not only present, but are up to...
Posted to
IC Packaging and SiP
(Weblog)
by
Jeff Gallagher
on Thu, Jan 17 2013
Be Among the First IC Packagers to Experience the New GDS-II Stream Interface in 16.6
For most IC package designers, the GDSII format is a part of daily life. You may receive stream data from your IC designers or partners which you must convert into die components for placement on a package substrate, or perhaps you export stream data as part of your manufacturing and documentation process...
Posted to
IC Packaging and SiP
(Weblog)
by
Jeff Gallagher
on Thu, Dec 20 2012
Leverage System Planning to Maximize Performance of Silicon Interposer
Recently, an article was published in Chip Scale Review by Cadence product manager Kevin Rinebold talking about maximizing the value of silicon interposer technology using system planning (see page 30). Today’s semiconductor technologies help meet the challenges of developing electronic products...
Posted to
IC Packaging and SiP
(Weblog)
by
TeamAllegro
on Thu, Dec 6 2012
What's Good About RF SiP and Data Management? Look to 16.6 and See!
The 16.6 Allegro RF SiP product has 3 major enhancements to improve your productivity. Read on for more details … Data Management of Virtuoso SiP Views In release 16.6, Virtuoso SiP Architect is enhanced to support data management of SiP views through the Virtuoso Library Manager. To enable this...
Posted to
PCB Design
(Weblog)
by
Jerry GenPart
on Tue, Dec 4 2012
Minimize Your Mouse Clicks in IC Packaging with New Customizable Wire Bond Application Mode in 16.6
Whether it is reducing mouse clicks, minimizing access to menus, eliminating the need to modify the find filter, or providing direct access to change options panel settings without leaving the canvas, anything that can be done to improve the efficiency of your design flow saves you time. And saving time...
Posted to
IC Packaging and SiP
(Weblog)
by
Jeff Gallagher
on Tue, Dec 4 2012
Open Cavity Design Tools for IC Packaging Now Available in 16.6
In version 16.5 of the Cadence IC package layout tools, we introduced embedded discrete component support. With the 16.6 release, that support has been extended even further. You are now able to define both manual and automatically-managed open cavities in which you can place your dies and die stacks...
Posted to
IC Packaging and SiP
(Weblog)
by
Jeff Gallagher
on Tue, Nov 27 2012
What's Good About APD’s Shape Shorting? You’ll Need the 16.6 Release to See!
In some designsflows, you need to connect two plane shapes on the same net, but on different layers, together with vias in order to improve connectivity. These “shorting” vias are placed in a regular pattern across the overlapping areas of the shape, in such a way as not to interfere with...
Posted to
PCB Design
(Weblog)
by
Jerry GenPart
on Tue, Nov 13 2012
Why Cadence Bought Sigrity – And How it May Change PCB Analysis
On July 2 Cadence announced its acquisition of Sigrity , a provider of signal integrity and power network analysis tools for PCB and IC package design. Cadence already has some technology in these areas, and many Allegro and OrCAD customers use Sigrity tools today. So why buy Sigrity, and why make this...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Jul 12 2012
What's Good About APD’s Wirebond Color Visibility? You’ll Need the 16.5 Release to See!
Prior to the 16.0 release, color and visibility (CV) settings of bond wires in Allegro Package Designer were based on the traditional layer model whereby wires were represented as 2-dimensional cline objects that could be colored and made visible or invisible depending on the layer they were on. In 16...
Posted to
PCB Design
(Weblog)
by
Jerry GenPart
on Tue, May 22 2012
What's Good About APD’s Symbol Editor App Mode? You’ll Need the 16.5 Release to See!
In an IC package design, it is common for the designer to customize the BGA component, or even the die components (if they are still subject to changes by the IC owner) in order to optimize the package substrate for cost and efficiency. In order to do this, changes to the components and physical symbols...
Posted to
PCB Design
(Weblog)
by
Jerry GenPart
on Tue, Mar 20 2012
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