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IC Packaging
"PCB design"
16.6
2.5D
3D-IC
advanced package designer
Advanced Package Router
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Help Shape Future Releases of APD and SiP – Provide Your Feedback on Early Adopter Features!
With every new release of the Cadence IC Package design software, many new features requested by designers are added. In other cases, interesting concepts that R&D engineers think up also make it into this list, so that real designers can try them out and suggest how they might work in a complex...
Posted to
IC Packaging and SiP
(Weblog)
by
Jeff Gallagher
on Mon, May 20 2013
Turn GDSII Data into Intelligent Die Components with 16.6 Cadence APD/SiP Tools
As we all know, there are many file formats in which an IC package designer will receive a die from the IC designer. Ideally, it will be in a format such as die text or a co-design die abstract, as these files contain both logical and physical information in a single, comprehensive file. Reality is often...
Posted to
IC Packaging and SiP
(Weblog)
by
Jeff Gallagher
on Fri, May 3 2013
Corral Your Selections with New Lasso and Path Modes in 16.6 APD and SiP
The level of ease and efficiency you experience in selecting the items needed for modifying in your substrate can mean the difference between a great design experience and an exercise in frustration and futility. With the 16.6 release, Cadence IC Packaging tools now offer an extended array of selection...
Posted to
IC Packaging and SiP
(Weblog)
by
Jeff Gallagher
on Thu, Apr 11 2013
CDNLive Silicon Valley 2013 Proceedings Available for Download!
CDNLive Silicon Valley, held March 12-13, 2013, featured nearly 100 technical sessions from customers, partners, and Cadence R&D experts. Presentations from most of those sessions are now available on line . Here's your chance to review presentations you heard, catch up on sessions you missed...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Apr 4 2013
Reduce Flip-Chip Design Time with Cadence Advanced Package Router (APR) for 16.6 APD and SiP Layout
Perhaps the most time-consuming aspect to designing the package substrate for a large, high pin count flip-chip comes in the form of package routing. Escaping from underneath the flip-chip die itself, routing through multiple substrate layers, and finally connecting to the assigned BGA balls might easily...
Posted to
IC Packaging and SiP
(Weblog)
by
Jeff Gallagher
on Thu, Mar 21 2013
What's Good About Allegro Package Designer (APD) Bond Wire "Text In?" You’ll Need the 16.6 Release to See!
Cadence IC Packaging tools today provide a spreadsheet-based import mechanism for die and BGA (standard) components, as well as for importing of netlist updates. In certain design scenarios, particularly for leadframe package designs, it is also desirable to be able to import a similarly formatted file...
Posted to
PCB Design
(Weblog)
by
Jerry GenPart
on Tue, Mar 19 2013
Remove Die Stack Layers from NC Drill Outputs using Cadence 16.6 SiP and APD IC Packaging Tools
As we continue with our series on improvements to the manufacturing and documentation outputs in the Cadence 16.6 IC Packaging layout tools, our focus this week is on NC Drill outputs. For as long as NC Drill data has been a part of the IC Packaging tools, and the cross-sections in package designs have...
Posted to
IC Packaging and SiP
(Weblog)
by
Jeff Gallagher
on Fri, Mar 1 2013
Allegro Sigrity Makes its Debut at DesignCon 2013
After Cadence acquired Sigrity in July 2012, we heard many of the same questions: What is happening with my favorite Sigrity tools? Is Cadence going to change the functions and features I’ve been working with several years? If I’m not a Cadence Allegro user, can I continue using Sigrity tools...
Posted to
PCB Design
(Weblog)
by
TeamAllegro
on Tue, Feb 12 2013
Ease Your IC Packaging Documentation and Manufacturing Exports for Stacked Dies in 16.6 SiP
Following our last posting concerning intelligent documentation text, this week we look at the a new ability in 16.6 for managing the die outlines in a manner which allows simplified generation of documentation and manufacturing outputs. In a complex IC package substrate, all die components may not be...
Posted to
IC Packaging and SiP
(Weblog)
by
Jeff Gallagher
on Wed, Feb 6 2013
How PCB and IC Package Design Can Enable “Product Creation”
My last blog post introduced the notion of "product creation," which looks beyond the chip and the board - the traditional focal points of EDA - to also consider software, mechanical enclosures, and everything else required to produce an actual product by semiconductor vendors and OEMs. That...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Feb 5 2013
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