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IC 6.1
A/MS
ADE
ADE-GXL
ADE-XL
advanced node
AMS
AMS Designer
AMS Verification
AMS-Designer
analog
Analog Design Environment
analog behavioral models
analog behavoral
Analog Design Environment
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analog/mixed-signal
APS
ARM
ARM Cortex M0
ARM-Cortex-M
Bleasdale
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CDNLive SV 2012
CDNLive!
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Circuit Design
Cliosoft
CMP
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Connectivity-driven
Constraint-driven
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Corners analysis
Cortex-M
Cortex-M0
CPF
Cusstom IC Design
Custom IC Design
custom/analog
design implementation
DFM
DFY
drag and drop
ECO
ECOs
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EDI
EDIS
Encounter
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IC 6.1.4
IC 6.1.5
IC615
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mixed signal design
mixed-signal
oa
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SKILL
SKILL++
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Spectre
STA
static timing analysis
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TowerJazz
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Variability Aware Design
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Verilog-AMS
Virtuoso
Virtuoso Advanced Node
Virtuoso Analog Design Environment
VIrtuoso drag and drop
Virtuoso environment
Virtuoso IC 6.1.3
Virtuoso IC6.1.5
Virtuoso Layout Suite GXL
Virtuoso Space-based Router
Virtuoso-AMS
Viva
ViVa-XL
VSR
worst case corners
Virtuosity: 10 Things I Learned in February By Browsing Cadence Online Support
February was a big month for RAKs (Rapid Adoption Kits)! If you haven't checked out the listings under Resources->Rapid Adoption Kits yet, you're missing out. You'll find databases with detailed instructions, documentation and videos on many tools, features and flows. They've become...
Posted to
Custom IC Design
(Weblog)
by
stacyw
on Mon, Mar 18 2013
Things You Didn't Know About Virtuoso: Drag and Drop
I love it when I'm sitting in a meeting with my colleagues or with a group of customers and someone brings up something about our software that they find annoying and another person says "Wait, why are you doing it that way? Why don't you just...". Immediately my mind says "blog...
Posted to
Custom IC Design
(Weblog)
by
stacyw
on Wed, Feb 13 2013
Mixed-Signal Technology Summit in Japan Provides Technology Updates
Japan’s semiconductor industry is undergoing a significant change in recent years. We are seeing a shrinking business in SoC development while design and semiconductor companies are trying to focus more on higher profitable and differentiable products like microcontrollers and power management...
Posted to
Mixed-Signal Design
(Weblog)
by
QiWang
on Thu, Nov 29 2012
A Quick Tutorial on Managing ECOs Using Pcells in Mixed Signal Designs
The purpose for creating a Pcell is to automate the creation of data. Pcells should be designed as standalone entities, independent of the environment in which they are created and independent of the variety of environments in which you or someone else might want to use them. An environment can react...
Posted to
Mixed-Signal Design
(Weblog)
by
paragb
on Wed, May 16 2012
Things You Didn't Know About Virtuoso: Change is Here to Stay
Speaking of variation -- and isn't everyone these days -- something strikes me in reading about all the powerful and elegant features of corners management and statistical analysis. After all the simulations are run and the results are presented, unless you've managed to hit a bullseye on the...
Posted to
Custom IC Design
(Weblog)
by
stacyw
on Thu, Apr 5 2012
Learn How to Do Mixed-Signal Design at CDNLive! Silicon Valley
With the theme of Connect, Share and Inspire, this year's CDNLive! Silicon Valley March 13-14, 2012 will be an exciting forum for Cadence customers to share their most recent chip design successes and learn from each other. Among close to 100 presentations during the packed two day agenda, one area...
Posted to
Mixed-Signal Design
(Weblog)
by
QiWang
on Wed, Mar 7 2012
Things You Didn't Know About Virtuoso: Measurements Across Corners
In Virtuoso IC 6.1.5 ISR6, we released a new feature in ADE XL, which had been requested by many customers--the ability to define a measurement expression which operates on the results of another measurement expression across corners. For example, I can create an expression to measure, say, a delay....
Posted to
Custom IC Design
(Weblog)
by
stacyw
on Thu, Feb 9 2012
Mixed-Signal Physical Design Implementation Made Easy
Getting a complex mixed-signal design assembled and completely analyzed for mask design is a huge challenge today. The IPs are complex and too many decisions need to be made to meet design budgets. All this is not possible with anything less than a fully automated, front-to-back mixed-signal design solution...
Posted to
Mixed-Signal Design
(Weblog)
by
RajendraPratap
on Thu, Jun 16 2011
Virtuoso Analog Design Environment XL – Make Friends with Variation
In my last blog, Virtuoso Analog Design Environment XL - Embrace the Productivity , I wrote about Virtuoso Analog Design Environment XL's multi-test bench environment and how design teams can make use of this feature to increase productivity and use hardware resources efficiently. In this blog, I...
Posted to
Custom IC Design
(Weblog)
by
Rama Jupalli
on Thu, Jun 16 2011
Thing You Didn't Know About Virtuoso: Redux
After a long break, I'm going to try to venture back into the blogosphere, starting off nice and easy--by cheating... You see, Virtuoso IC 6.1.5 came out at the end of January, and one of the changes made to the Schematic Editor is that many of the handy dockable assistants featured in IC 6.1 are...
Posted to
Custom IC Design
(Weblog)
by
stacyw
on Wed, Apr 27 2011
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